{"title":"用于设计、验证和综合大规模异步系统的状态图方法","authors":"Rakefet Kol, R. Ginosar, G. Samuel","doi":"10.1109/ASYNC.1996.494448","DOIUrl":null,"url":null,"abstract":"We apply a novel methodology, based on statecharts, for the design of large scale asynchronous systems. The EXV CAD tool offers specification at multiple levels, simulation, animation, and compilation into synthesizable VHDL code. EXV has some verification capabilities, and we add a validation sub-system EXV is originally synchronous, but we discuss how to employ it for asynchronous design. The tool is demonstrated through a simple FSM.","PeriodicalId":365358,"journal":{"name":"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems\",\"authors\":\"Rakefet Kol, R. Ginosar, G. Samuel\",\"doi\":\"10.1109/ASYNC.1996.494448\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We apply a novel methodology, based on statecharts, for the design of large scale asynchronous systems. The EXV CAD tool offers specification at multiple levels, simulation, animation, and compilation into synthesizable VHDL code. EXV has some verification capabilities, and we add a validation sub-system EXV is originally synchronous, but we discuss how to employ it for asynchronous design. The tool is demonstrated through a simple FSM.\",\"PeriodicalId\":365358,\"journal\":{\"name\":\"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-03-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASYNC.1996.494448\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASYNC.1996.494448","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems
We apply a novel methodology, based on statecharts, for the design of large scale asynchronous systems. The EXV CAD tool offers specification at multiple levels, simulation, animation, and compilation into synthesizable VHDL code. EXV has some verification capabilities, and we add a validation sub-system EXV is originally synchronous, but we discuss how to employ it for asynchronous design. The tool is demonstrated through a simple FSM.
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