2014 Formal Methods in Computer-Aided Design (FMCAD)最新文献

2014 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987601

A. Gurfinkel, Y. Vizel

{"title":"DRUPing for interpolates","authors":"A. Gurfinkel, Y. Vizel","doi":"10.1109/FMCAD.2014.6987601","DOIUrl":"https://doi.org/10.1109/FMCAD.2014.6987601","url":null,"abstract":"We present a method for interpolation based on DRUP proofs. Interpolants are widely used in model checking, synthesis and other applications. Most interpolation algorithms rely on a resolution proof produced by a SAT-solver for unsatisfaible formulas. The proof is traversed and translated into an interpolant by replacing resolution steps with AND and OR gates. This process is efficient (once there is a proof) and generates interpolants that are linear in the size of the proof. In this paper, we address three known weakness of this approach: (i) performance degradation experienced by the SAT-solver and the extra memory requirements needed when logging a resolution proof; (ii) the proof generated by the solver is not necessarily the \"best\" proof for interpolantion, and (iii) combining proof logging with pre-processing is complicated. We show that these issues can be remedied by using DRUP proofs. First, we show how to produce an interpolant from a DRUP proof, even when pre-processing is enabled. Second, we give a novel interpolation algorithm that produces interpolants partially in CNF. Third, we show how DRUP proof can be restructured on-the-fly to yield better interpolants. We implemented our DRUP-based interpolation framework in MiniSAT, and evaluated its affect using Avy - a SAT-based model checking algorithm.","PeriodicalId":363683,"journal":{"name":"2014 Formal Methods in Computer-Aided Design (FMCAD)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128494659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Simulation and formal verification of x86 machine-code programs that make system calls 进行系统调用的x86机器码程序的仿真和形式化验证

2014 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987600

Shilpi Goel, W. Hunt, Matt Kaufmann, Soumava Ghosh

{"title":"Simulation and formal verification of x86 machine-code programs that make system calls","authors":"Shilpi Goel, W. Hunt, Matt Kaufmann, Soumava Ghosh","doi":"10.1109/FMCAD.2014.6987600","DOIUrl":"https://doi.org/10.1109/FMCAD.2014.6987600","url":null,"abstract":"We present an approach to modeling and verifying machine-code programs that exhibit non-determinism. Specifically, we add support for system calls to our formal, executable model of the user-level x86 instruction-set architecture (ISA). The resulting model, implemented in the ACL2 theorem-proving system, allows both formal analysis and efficient simulation of x86 machine-code programs; the logical mode characterizes an external environment to support reasoning about programs that interact with an operating system, and the execution mode directly queries the underlying operating system to support simulation. The execution mode of our x86 model is validated against both its logical mode and the real machine, providing test-based assurance that our model faithfully represents the semantics of an actual x86 processor. Our framework is the first that enables mechanical proofs of functional correctness of user-level x86 machine-code programs that make system calls. We demonstrate the capabilities of our model with the mechanical verification of a machine-code program, produced by the GCC compiler, that computes the number of characters, lines, and words in an input stream. Such reasoning is facilitated by our libraries of ACL2 lemmas that allow automated proofs of a program's memory-related properties.","PeriodicalId":363683,"journal":{"name":"2014 Formal Methods in Computer-Aided Design (FMCAD)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129698822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 44

Post-silicon timing diagnosis made simple using formal technology 后硅定时诊断使得使用正式技术变得简单

2014 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987605

Daher Kaiss, Jonathan Kalechstain

引用次数: 7

Predicate abstraction for reactive synthesis 反应性合成的谓词抽象

2014 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987617

Adam Walker, L. Ryzhyk

引用次数: 23

Reduction for compositional verification of multi-threaded programs 减少多线程程序的组成验证

2014 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987612

C. Popeea, A. Rybalchenko, Andreas Wilhelm

引用次数: 15

Leveraging linear and mixed integer programming for SMT 利用SMT的线性和混合整数规划

2014 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987606

Tim King, Clark W. Barrett, C. Tinelli

{"title":"Leveraging linear and mixed integer programming for SMT","authors":"Tim King, Clark W. Barrett, C. Tinelli","doi":"10.1109/FMCAD.2014.6987606","DOIUrl":"https://doi.org/10.1109/FMCAD.2014.6987606","url":null,"abstract":"SMT solvers combine SAT reasoning with specialized theory solvers either to find a feasible solution to a set of constraints or to prove that no such solution exists. Linear programming (LP) solvers come from the tradition of optimization, and are designed to find feasible solutions that are optimal with respect to some optimization function. Typical LP solvers are designed to solve large systems quickly using floating point arithmetic. Because floating point arithmetic is inexact, rounding errors can lead to incorrect results, making inexact solvers inappropriate for direct use in theorem proving. Previous efforts to leverage such solvers in the context of SMT have concluded that in addition to being potentially unsound, such solvers are too heavyweight to compete in the context of SMT. In this paper, we describe a technique for integrating LP solvers that improves the performance of SMT solvers without compromising correctness. These techniques have been implemented using the SMT solver CVC4 and the LP solver GLPK. Experiments show that this implementation outperforms other state-of-the-art SMT solvers on the QF_LRA SMT-LIB benchmarks and is competitive on the QF_LIA benchmarks.","PeriodicalId":363683,"journal":{"name":"2014 Formal Methods in Computer-Aided Design (FMCAD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114672031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Efficient symbolic execution for software testing 有效的符号执行软件测试

2014 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987585

Johannes Kinder

引用次数: 0

Small inductive safe invariants 小的归纳安全不变量

2014 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987603

A. Ivrii, A. Gurfinkel, A. Belov

引用次数: 10

Challenging problems in industrial formal verification 工业形式验证中的挑战问题

2014 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987583

Z. Hanna

{"title":"Challenging problems in industrial formal verification","authors":"Z. Hanna","doi":"10.1109/FMCAD.2014.6987583","DOIUrl":"https://doi.org/10.1109/FMCAD.2014.6987583","url":null,"abstract":"Summary form only given. The electronic design industry has emerged in the recent years to adopt the system-on-chip (SoC) design methodology, where systems become a smart and complex integration of many configurable and reusable intellectual properties (IP) designs such as CPU, GPU, DSP, etc. SoC design methodologies have become common to a wide range of systems, starting from high-end servers, down to tablets, smartphones, Internet-of-things and wearable devices. The aggressive time-to-market and the hard competition add a major challenge to the electronic design companies to deliver high volume, and high quality products. Integration and validation of such designs has become the major challenge. The EDA industry and the academia has continued the innovation pipeline trying to cope with the complexity of such systems however major challenges are still ahead. Formal verification has emerged in the recent years to become a mainstream technology in SoC/IP design and verification methodologies. In the past, the usage of formal verification was limited to a small range of applications and it was mainly for verifying complex protocols, or some tricky logic functionality by formal experts. However in the recent years, we see a rapid adoption of formal, and we see a widespread of formal verification applications for low power design, security, SoC connectivity, configuration status register, and many more. In this talk, we provide an overview of the challenges that we see in designing SoC systems and configurable IPs, and provide some ideas to stimulate the academic research, aiming at increasing the research and innovation in such areas for keeping bridging the emerging gap that the electronic design industry is facing now and will face in the future.","PeriodicalId":363683,"journal":{"name":"2014 Formal Methods in Computer-Aided Design (FMCAD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116755138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Disproving termination with overapproximation 用过度近似否定终止

2014 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987597

B. Cook, Carsten Fuhs, K. Nimkar, P. O'Hearn

引用次数: 30