IEEE CPMT Symposium Japan 2014最新文献_第5页

IO interface for over 25Gbps operation with low power IO接口，可实现25Gbps以上的低功耗操作

IEEE CPMT Symposium Japan 2014 Pub Date : 2014-11-01 DOI: 10.1109/ICSJ.2014.7009615

K. Otsuka, F. Fujii, Y. Akiyama, K. Hashimoto

引用次数: 5

Threshold value estimation of electrical interconnect tests with scan FFs 带扫描FFs的电气互连测试阈值估计

IEEE CPMT Symposium Japan 2014 Pub Date : 2014-11-01 DOI: 10.1109/ICSJ.2014.7009634

Kousuke Nambara, Shoichi Umezu, H. Yotsuyanagi, M. Hashizume, Shyue-Kung Lu

引用次数: 1

High aspect ratio TSV etching process for high-capacitor 高电容高纵横比TSV蚀刻工艺

IEEE CPMT Symposium Japan 2014 Pub Date : 2014-11-01 DOI: 10.1109/ICSJ.2014.7009632

T. Murayama, T. Sakuishi, Y. Morikawa, N. Tani, K. Saitou

{"title":"High aspect ratio TSV etching process for high-capacitor","authors":"T. Murayama, T. Sakuishi, Y. Morikawa, N. Tani, K. Saitou","doi":"10.1109/ICSJ.2014.7009632","DOIUrl":"https://doi.org/10.1109/ICSJ.2014.7009632","url":null,"abstract":"TSV (Thru Silicon Via) application for 2.5D silicon interposers and 3D stacked devices is expected to realize a next-generation semiconductor device with high packaging density, power saving, and high-speed signal transmission, etc. Recently, discussions on long-term reliability of TSV has been triggered, the establishment of TSV integration technologies contribute to reliability is strongly requested to enable TSV packaging promote mass production. We have developed Si etching technology for high aspect ratio (>20) ultra low leak high-capacitor by using TSV production technology. As anisotropic deep silicon etching method, cycle etching and non-cycle etching method have been offered. Cycle etching is a general anisotropic Si etching method by cyclic etching of deposit (fluorocarbon polymer) and etching. In cycle etching, sidewall is protected by fluorocarbon polymer, periodic roughness appears on etched sidewall called “scallops”. On the other hand, non-cycle etching is without using fluorocarbon. In non-cycle etching, sidewall is protected by thin SiOX, non-cyclic etching process achieves smooth etched “scallops-free” sidewall. It is considered that the quality of etched sidewall influences capacitor reliability in process integration, it is necessary to investigate sidewall condition about both cycle etching and non-cycle/scallops-free etching because of differences of each etching process property; process gas, sidewall protection mechanism, scallops/scallopsfree, and so on. Therefore we conducted XPS analysis etched trench sidewall; depth of 10 um, 25 um, 40 um. It is showed that in cycle etching there are more residual F and C on etched sidewall due to fluorocarbon polymer than non-cycle without using fluorocarbon. It is considered that more residual F and C on etched sidewall might influence capacitor and TSV reliability.","PeriodicalId":362502,"journal":{"name":"IEEE CPMT Symposium Japan 2014","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129023890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Optical micro sensors integration and application 光学微传感器集成与应用

IEEE CPMT Symposium Japan 2014 Pub Date : 2014-11-01 DOI: 10.1109/ICSJ.2014.7009595

N. Morita, R. Sawada

引用次数: 2

On-board snubber circuit for damping of anti-resonance peak in total PDN 用于抑制总PDN抗共振峰的板载缓冲电路

IEEE CPMT Symposium Japan 2014 Pub Date : 2014-01-13 DOI: 10.1109/ICSJ.2014.7009617

T. Yamaguchi, Kanae Kurita, T. Sudo

引用次数: 5

Power-bus noise reduction using ferrite-covered open stub in printed circuit board 用铁氧体覆盖的印刷电路板开路短管降低电源母线噪声

IEEE CPMT Symposium Japan 2014 Pub Date : 2014-01-13 DOI: 10.1109/ICSJ.2014.7009614

Y. Toyota

引用次数: 0

Fabrication for low-loss polymer optical waveguides with 90° bending using the Mosquito method 用Mosquito法制备90°弯曲低损耗聚合物光波导

IEEE CPMT Symposium Japan 2014 Pub Date : 2014-01-13 DOI: 10.1109/ICSJ.2014.7009635

Asami Takahashi, T. Ishigure

引用次数: 6

Measurement and modeling for MOS reverse current of switching DC/DC converter 开关DC/DC变换器MOS反向电流的测量与建模

IEEE CPMT Symposium Japan 2014 Pub Date : 2014-01-13 DOI: 10.1109/ICSJ.2014.7009616

Masahiro Terasaki, Yuta Oohashi, Y. Masuyama, T. Sudo

{"title":"Measurement and modeling for MOS reverse current of switching DC/DC converter","authors":"Masahiro Terasaki, Yuta Oohashi, Y. Masuyama, T. Sudo","doi":"10.1109/ICSJ.2014.7009616","DOIUrl":"https://doi.org/10.1109/ICSJ.2014.7009616","url":null,"abstract":"DC/DC converters are widely used to produce various power supply voltages required for various electronic components on a board. Though DC/DC converter is more efficient than the linear regulator is, however, the switching noise becomes larger with the increase of the switching frequency. In particular, ringing noises at the sharp rising edge of the switching waveform generated by the effect of the parasitic inductance becomes a serious issue. This noise spreads out to the whole circuit board, and then generates electromagnetic interference (EMI), which often causes a malfunction of the electronic systems. In this paper, the methods to accurately reproduce the switching waveforms and to reduce ringing noises and resulting EMI from DC/DC converters were investigated. For this purpose, several evaluation boards were designed, and total electrical model was constructed by taking into account the parasitic inductances of traces on a board. First, frequency-domain analysis for the switching loop of the DC/DC converters was executed to find the optimum condition to suppress ringing noise effectively. Next, time-domain simulation was executed by considering the recovering time of MOS reverse current, which is not provided from device vendors. Finally, measured switching waveforms were well correlated with the simulated ones, and the optimal condition to suppress the ringing noise.","PeriodicalId":362502,"journal":{"name":"IEEE CPMT Symposium Japan 2014","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121605022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Plenary invited 全体邀请

IEEE CPMT Symposium Japan 2014 Pub Date : 1900-01-01 DOI: 10.1109/icsj.2015.7357342

Interposers Yasuhiko Arakawa, S. Shoji

引用次数: 0