High aspect ratio TSV etching process for high-capacitor

Abstract

TSV (Thru Silicon Via) application for 2.5D silicon interposers and 3D stacked devices is expected to realize a next-generation semiconductor device with high packaging density, power saving, and high-speed signal transmission, etc. Recently, discussions on long-term reliability of TSV has been triggered, the establishment of TSV integration technologies contribute to reliability is strongly requested to enable TSV packaging promote mass production. We have developed Si etching technology for high aspect ratio (>20) ultra low leak high-capacitor by using TSV production technology. As anisotropic deep silicon etching method, cycle etching and non-cycle etching method have been offered. Cycle etching is a general anisotropic Si etching method by cyclic etching of deposit (fluorocarbon polymer) and etching. In cycle etching, sidewall is protected by fluorocarbon polymer, periodic roughness appears on etched sidewall called “scallops”. On the other hand, non-cycle etching is without using fluorocarbon. In non-cycle etching, sidewall is protected by thin SiOX, non-cyclic etching process achieves smooth etched “scallops-free” sidewall. It is considered that the quality of etched sidewall influences capacitor reliability in process integration, it is necessary to investigate sidewall condition about both cycle etching and non-cycle/scallops-free etching because of differences of each etching process property; process gas, sidewall protection mechanism, scallops/scallopsfree, and so on. Therefore we conducted XPS analysis etched trench sidewall; depth of 10 um, 25 um, 40 um. It is showed that in cycle etching there are more residual F and C on etched sidewall due to fluorocarbon polymer than non-cycle without using fluorocarbon. It is considered that more residual F and C on etched sidewall might influence capacitor and TSV reliability.