1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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A 45k HEMT Gate Array With 35ps DCFL And 50ps BDCFL Gates 具有35ps DCFL和50ps BDCFL门的45k HEMT门阵列
S. Notomi, T. Kondo, Y. Watanabe, M. Kosugi, S. Hanyu, M. Suzuki, A. Kaneko, T. Mimura, M. Abe
{"title":"A 45k HEMT Gate Array With 35ps DCFL And 50ps BDCFL Gates","authors":"S. Notomi, T. Kondo, Y. Watanabe, M. Kosugi, S. Hanyu, M. Suzuki, A. Kaneko, T. Mimura, M. Abe","doi":"10.1109/ISSCC.1991.689105","DOIUrl":"https://doi.org/10.1109/ISSCC.1991.689105","url":null,"abstract":"","PeriodicalId":360958,"journal":{"name":"1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115071881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 45ns 64Mb DRAM With A Merged Match-line Test Architecture 具有合并匹配线测试架构的45ns 64Mb DRAM
S. Mori, H. Miyamoto, Y. Morooka, S. Kikuda, M. Suwa, M. Kinoshita, A. Hachisuka, H. Arima, M. Yamada, T. Yoshihara, S. Kayano
{"title":"A 45ns 64Mb DRAM With A Merged Match-line Test Architecture","authors":"S. Mori, H. Miyamoto, Y. Morooka, S. Kikuda, M. Suwa, M. Kinoshita, A. Hachisuka, H. Arima, M. Yamada, T. Yoshihara, S. Kayano","doi":"10.1109/isscc.1991.689085","DOIUrl":"https://doi.org/10.1109/isscc.1991.689085","url":null,"abstract":"","PeriodicalId":360958,"journal":{"name":"1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122423479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Zero-overhead Self-timed 160ns 54b CMOS Divider 零开销自定时160ns 54b CMOS分频器
T. E. Williarns, M. Horowitz
{"title":"A Zero-overhead Self-timed 160ns 54b CMOS Divider","authors":"T. E. Williarns, M. Horowitz","doi":"10.1109/isscc.1991.689080","DOIUrl":"https://doi.org/10.1109/isscc.1991.689080","url":null,"abstract":"This circuit demonstrates a self-timed iterating ring which attains the speed of a combinational array while using only a fraction of the silicon area. The stages in the ring compute mantissa quotient digits for a floating-point division operation. Unlike circuits which implement self-timing by using a matched on-chip clock generator to provide an internal clock for synchronous blocks, the circuit of this paper uses local control handshaking between fully asynchronous blocks and will operate correctly for any values of gate delays.' To avoid embedded in the data throughout the design by using dual-requiring matching path delays, complction information is monotonic wire pairs. The precharged function blocks use merged n-channel pull-down networks to choose which of thc wires in each pair to set high. nous pipeline by looping data from its output back to its input. A self-timed iterating ring is formed from an asynchro-The total latency and throughput tradeoff with the number of latches in the ring? Minimallatency is achievcdinthis chip by directly concatenating precharged logic blocks into a looped domino chain without adding any explicit latches. The prc-charge (reset) signals for each block are controlled separately so each block can be used as an implicit latch without adding any additional transistors. The self-timed control is designed to precharge each block after data passes it, and to remove its precharge enabling its evaluation, before data loops around to its inputs again. A graph-based method is used to analyze the inter-block dependencies and aids in keeping the critical path solely within the combinational data elements. of which is internally composed of precharged blocks. .4 key t o Theringisorganizedasaseriesofadjoiningstageseach removing extra control dependencies which could degrade utilize and encompass the time taken by lhecontrol so its delay performance is t o place enough stages in the loop to fully is completely hidden. This chip uses five stages to allow the control signals to enable each block 0.7 stage delays before its data arrives, which is measured at 211s as shown in Figure 1. This margin ensures no control logic enters into the critical path even with some variances in the delays. Thus, the data flow continually at the same rate it would flow through an \" unwrapped \" combinational array implementing the same functions. While most previous asynchronous circuits have suffered delays due to handshaking and control, this methodof self-timing adds zero control overhead to the latency of the raw function computation. …","PeriodicalId":360958,"journal":{"name":"1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130431422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
A Multirate Transceiver IC For Four-wire Full Duplex Data Transmission 用于四线全双工数据传输的多速率收发器IC
K. Buttle, H. Takatori, C. Shih, H. Shafir
{"title":"A Multirate Transceiver IC For Four-wire Full Duplex Data Transmission","authors":"K. Buttle, H. Takatori, C. Shih, H. Shafir","doi":"10.1109/ISSCC.1991.689140","DOIUrl":"https://doi.org/10.1109/ISSCC.1991.689140","url":null,"abstract":"","PeriodicalId":360958,"journal":{"name":"1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115131039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 60ns 16Mb Flash EEPROM With Program And Erase Sequence Controller 带有程序和擦除顺序控制器的60ns 16Mb闪存EEPROM
T. Nakayama, S. Kobayashi, Y. Miyawaki, Y. Terada, N. Alika, M. Chi, H. Arima, T. Matsukawa, T. Yoshihara
{"title":"A 60ns 16Mb Flash EEPROM With Program And Erase Sequence Controller","authors":"T. Nakayama, S. Kobayashi, Y. Miyawaki, Y. Terada, N. Alika, M. Chi, H. Arima, T. Matsukawa, T. Yoshihara","doi":"10.1109/ISSCC.1991.689151","DOIUrl":"https://doi.org/10.1109/ISSCC.1991.689151","url":null,"abstract":"","PeriodicalId":360958,"journal":{"name":"1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114811423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 336-neuron 28k-synapse Self-learning Neural Network Chip With Branch-neuron-unit Architecture 基于分支神经元单元结构的336个神经元28k突触自学习神经网络芯片
Y. Arima, K. Mashiko, K. Okada, T. Yamada, A. Maeda, H. Notani, H. Kondoh, S. Kayano
{"title":"A 336-neuron 28k-synapse Self-learning Neural Network Chip With Branch-neuron-unit Architecture","authors":"Y. Arima, K. Mashiko, K. Okada, T. Yamada, A. Maeda, H. Notani, H. Kondoh, S. Kayano","doi":"10.1109/ISSCC.1991.689118","DOIUrl":"https://doi.org/10.1109/ISSCC.1991.689118","url":null,"abstract":"","PeriodicalId":360958,"journal":{"name":"1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134378190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
DC - 10GHz Mixer And Amplifier GaAs ICs For Coherent Optical Heterodyne Receiver 用于相干光外差接收机的DC - 10GHz混频器和放大器GaAs集成电路
S. Fujita, Y. Imai, Y. Yamane, H. Fushimi
{"title":"DC - 10GHz Mixer And Amplifier GaAs ICs For Coherent Optical Heterodyne Receiver","authors":"S. Fujita, Y. Imai, Y. Yamane, H. Fushimi","doi":"10.1109/ISSCC.1991.689090","DOIUrl":"https://doi.org/10.1109/ISSCC.1991.689090","url":null,"abstract":"","PeriodicalId":360958,"journal":{"name":"1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128439751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 30MHz Trellis CODEC Chip For Partial-response Channels 用于部分响应信道的30MHz栅格编解码器芯片
C. Shung, P. Siegel, H. Thapar, R. Karabed
{"title":"A 30MHz Trellis CODEC Chip For Partial-response Channels","authors":"C. Shung, P. Siegel, H. Thapar, R. Karabed","doi":"10.1109/ISSCC.1991.689094","DOIUrl":"https://doi.org/10.1109/ISSCC.1991.689094","url":null,"abstract":"","PeriodicalId":360958,"journal":{"name":"1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116807154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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