A Zero-overhead Self-timed 160ns 54b CMOS Divider

Abstract

This circuit demonstrates a self-timed iterating ring which attains the speed of a combinational array while using only a fraction of the silicon area. The stages in the ring compute mantissa quotient digits for a floating-point division operation. Unlike circuits which implement self-timing by using a matched on-chip clock generator to provide an internal clock for synchronous blocks, the circuit of this paper uses local control handshaking between fully asynchronous blocks and will operate correctly for any values of gate delays.' To avoid embedded in the data throughout the design by using dual-requiring matching path delays, complction information is monotonic wire pairs. The precharged function blocks use merged n-channel pull-down networks to choose which of thc wires in each pair to set high. nous pipeline by looping data from its output back to its input. A self-timed iterating ring is formed from an asynchro-The total latency and throughput tradeoff with the number of latches in the ring? Minimallatency is achievcdinthis chip by directly concatenating precharged logic blocks into a looped domino chain without adding any explicit latches. The prc-charge (reset) signals for each block are controlled separately so each block can be used as an implicit latch without adding any additional transistors. The self-timed control is designed to precharge each block after data passes it, and to remove its precharge enabling its evaluation, before data loops around to its inputs again. A graph-based method is used to analyze the inter-block dependencies and aids in keeping the critical path solely within the combinational data elements. of which is internally composed of precharged blocks. .4 key t o Theringisorganizedasaseriesofadjoiningstageseach removing extra control dependencies which could degrade utilize and encompass the time taken by lhecontrol so its delay performance is t o place enough stages in the loop to fully is completely hidden. This chip uses five stages to allow the control signals to enable each block 0.7 stage delays before its data arrives, which is measured at 211s as shown in Figure 1. This margin ensures no control logic enters into the critical path even with some variances in the delays. Thus, the data flow continually at the same rate it would flow through an " unwrapped " combinational array implementing the same functions. While most previous asynchronous circuits have suffered delays due to handshaking and control, this methodof self-timing adds zero control overhead to the latency of the raw function computation. …