Int. J. Embed. Real Time Commun. Syst.最新文献

{"title":"Application Workload Modelling via Run-Time Performance Statistics","authors":"Subayal Khan, Jukka Saastamoinen, J. Huusko, J. Soininen, J. Nurmi","doi":"10.4018/JERTCS.2013040101","DOIUrl":"https://doi.org/10.4018/JERTCS.2013040101","url":null,"abstract":"Modern mobile nomadic devices for example internet tablets and high end mobile phones support diverse distributed and stand-alone applications that were supported by single devices a decade back. Furthermore the complex heterogeneous platforms supporting these applications contain multi-core processors, hardware accelerators and IP cores and all these components can possibly be integrated into a single integrated circuit chip. The high complexity of both the platform and the applications makes the design space very complex due to the availability of several alternatives. Therefore the system designer must be able to quickly evaluate the performance of different application architectures and implementations on potential platforms. The most popular technique employed nowadays is termed as system-level-performance evaluation which uses abstract workload and platform capacity models. The platform capacity models and application workload models reside at a higher abstraction-level. The platform and application workload models can be instantiated with reduced modeling effort and also operate at a higher simulation speed. This article presents a novel run-time statistics based application workload model extraction and platform configuration technique. This technique is called platform COnfiguration and woRkload generatIoN via code instrumeNtation and performAnce counters CORINNA which offers several advantages over compiler based technique called ABSINTH, and also provides automatic configuration of the platform processor models for example cache-hits and misses obtained during the application execution.","PeriodicalId":359507,"journal":{"name":"Int. J. Embed. Real Time Commun. Syst.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122678671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative Caches","authors":"Y. Chu, M. Calagos","doi":"10.4018/jertcs.2013040103","DOIUrl":"https://doi.org/10.4018/jertcs.2013040103","url":null,"abstract":"This paper proposes a buffered dual-access-mode cache to reduce power consumption for highly-associative caches in modern embedded systems. The proposed scheme consists of a MRU most recently used buffer table and a single cache structure to implement two accessing modes, phased mode and way-prediction mode. The proposed scheme shows better access time and lower power consumption than two popular low-power caches, phased cache and way-prediction cache. The authors used Cacti and SimpleScalar simulators to evaluate the proposed cache scheme by using SPEC benchmark programs. The experimental results show that the proposed cache scheme improves the EDP energy delay product up to 40% for instruction cache and up to 42% for data cache compared to way-prediction cache, which performs better than phased cache.","PeriodicalId":359507,"journal":{"name":"Int. J. Embed. Real Time Commun. Syst.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126247356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Power and Latency Optimized Deadlock-Free Routing Algorithm on Irregular 2D Mesh NoC using LBDRe","authors":"R. Verma, Mohammad Ayoub Khan, Amit Zinzuwadiya","doi":"10.4018/jertcs.2013040102","DOIUrl":"https://doi.org/10.4018/jertcs.2013040102","url":null,"abstract":"Efficient routing is challenging and crucial problem in the irregular mesh NoC topologies because of increasing hardware cost and routing tables. In this paper, the authors propose an efficient deadlock-free routing algorithm for irregular mesh NoCs which reduces the latency and power consumption significantly. The problem with degree priority based routing algorithm is that it cannot remove deadlocks in irregular mesh topologies. Therefore, the authors use the extended Logic Based Distributed Routing LBDRe to remove deadlock situations without using any virtual channel in the degree priority based routing algorithm. The proposed LBDRe based technique also removes the dependency on routing tables. The authors further apply odd-Even routing algorithm to LBDRe to ensure that some turns are prohibited to remove deadlocks. Experimental results show that the proposed routing algorithm reduces power consumption by 9-22% and overall average latency by 8-12% with the minimum hardware cost for the irregular mesh NoC topologies.","PeriodicalId":359507,"journal":{"name":"Int. J. Embed. Real Time Commun. Syst.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131345748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"International Symposium on System-on-Chip 2011","authors":"J. Nurmi","doi":"10.4018/JERTCS.2012100105","DOIUrl":"https://doi.org/10.4018/JERTCS.2012100105","url":null,"abstract":"","PeriodicalId":359507,"journal":{"name":"Int. J. Embed. Real Time Commun. Syst.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122130499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance Analysis of Temperature Management Approaches in Networks-on-Chip","authors":"Tim Wegner, Martin Gag, D. Timmermann","doi":"10.4018/jertcs.2012100102","DOIUrl":"https://doi.org/10.4018/jertcs.2012100102","url":null,"abstract":"With the progress of deep submicron technology, power consumption and temperature related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management. On the other hand, application of thermal management is accompanied by disturbance of system integrity and degradation of system performance. In this paper the authors propose to precompute and proactively manage on-chip temperature of systems based on Networks-on-Chip (NoCs). Thereby, traditional reactive approaches, utilizing the NoC infrastructure to perform thermal management, can be replaced. This results not only in shorter response times for application of management measures and a reduction of temperature and thermal imbalances, but also in less impairment of system integrity and performance. The systematic analysis of simulations conducted for NoC sizes ranging from 2x2 to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile. DOI: 10.4018/jertcs.2012100102 20 International Journal of Embedded and Real-Time Communication Systems, 3(4), 19-41, October-December 2012 Copyright © 2012, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited. the integrity of Integrated Circuits (ICs) and have major influence on operability, lifetime and performance. The relationship between temperature and deterioration is illustrated by the Arrhenius model (Srinivasan & Adve, 2003) describing the influence of temperature on the velocity of chemical reactions. This model originates from the Van’t Hoff rule also known as the reaction rate temperature rule (or RGT rule), saying that chemical reactions take place twice as fast when temperature is increased by 10 K. As a rule of thumb, this also can be interpreted as a bisection of lifetime of ICs with every 10 K temperature increase. For this reason, monitoring and control of on-chip temperature distribution are important tasks to secure system functionality and ensure high performance. Typically, monitoring of on-chip temperature is performed by collecting temperaturerelated data (e.g., by using integrated diodes). In order to react to undesirable temperatures this data has to be transferred to a component responsible for data evaluation and determination of appropriate reactions (i.e., thermal management). Then instructions are sent to the concerned components. For NoC-based systems, commonly the NoC infrastructure is used for this communication. Despite the importance of thermal management, reactive approaches impair system performance, since the utilization of the NoC presents an intrusion into the system and the induced traffic curtails the availability of the N","PeriodicalId":359507,"journal":{"name":"Int. J. Embed. Real Time Commun. Syst.","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116884631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience","authors":"M. Krstic, Xin Fan, E. Grass, L. Benini, M. R. Kakoee, C. Heer, Birgit Sanders, Alessandro Strano, D. Bertozzi","doi":"10.4018/jertcs.2012100101","DOIUrl":"https://doi.org/10.4018/jertcs.2012100101","url":null,"abstract":"In this paper the authors present the concept and evaluation results of a complex GALS ASIC demonstrator in 40 nm CMOS process. This chip, named Moonrake, compares synchronous and GALS synchronization technology in a homogeneous experimental setting: same baseline designs, same manufacturing process, same die. The chip validates GALS technology for both point-to-point and network-centric on-chip communications, demonstrating its potentials for different applications. The design analysis, measurement and test results confirm the potential of GALS approach for the scaled technologies, showing the significant benefits in respect to area, power, and EMI when it comes to the complex system implementation. Furthermore, 91% of the tests performed on the GALS network-on-chip test structures completed successfully, validating the timing robustness of new area and latency-efficient synchronization schemes and proving that the design flow for GALS synchronization technology can be implemented by means of mainstream industrial tools. DOI: 10.4018/jertcs.2012100101 2 International Journal of Embedded and Real-Time Communication Systems, 3(4), 1-18, October-December 2012 Copyright © 2012, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited. INTRODUCTION Globally Asynchronous Locally Synchronous (GALS) technology has been proposed many years ago as an alternative to the traditional synchronous paradigm for chip synchronization (Krstic, 2006). Although significant potential was reported by the academia, the GALS methodology has never taken off in the industry. However, the growing challenges, imposed by the unrelenting pace of technology scaling to the nanoscale regime, urge for an efficient and safe system-level integration methodology. Consequently, we have targeted the implementation of a chip, named Moonrake, in the advanced 40 nm CMOS process, aiming at the assessment of GALS technology for nanoscale designs. Our intention was to evaluate GALS vs. standard synchronous technology on the same die, by implementing synchronous and GALS counterparts of the same baseline designs, both in the point-to-point as well as in the networkon-chip (NoC) scenarios for on-chip communication. The two scenarios are very different, hence motivating the different choice of baseline designs for their analysis. In point-to-point communication, once an optimized GALS interface is selected, the focus is on the implications of redesigning an entire system around these links. In this direction, we took a state-of-theart multi-million gate synchronous system, an OFDM baseband transmitter developed for a 60 GHz transceiver with a gigabit throughput as presented by Krstic in 2008, and re-implemented it with GALS methodology, using the optimized interfaces for pausible (stoppable) clocking as defined by Fan in 2009. One major goal was to explore Electromagnetic Interference (EMI) and switching noise properties of GALS de","PeriodicalId":359507,"journal":{"name":"Int. J. Embed. Real Time Commun. Syst.","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115190098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links","authors":"S. Höppner, D. Walter, G. Ellguth, R. Schüffny","doi":"10.4018/jertcs.2012100103","DOIUrl":"https://doi.org/10.4018/jertcs.2012100103","url":null,"abstract":"This paper presents techniques for measurement and compensation of timing variations in clock and data channels of source-synchronous high-speed serial network-on-chip (NoC) links. Timing mismatch measurements are performed by means of asynchronous sub-sampling. This allows the use of low quality sampling clocks to reduce test hardware overhead for integration into complex MPSoCs (Multiprocessor System-on-Chip) with multiple NoC links. The effect of clock jitter on the measurement results is evaluated. Delay mismatch is compensated by tunable delay cells. The proposed technique enables compensation of delay variations to realize high-speed NoC links with sufficient yield. It is demonstrated at NoC links as part of an MPSoC in 65 nm Complementary Metal Oxide Semiconductor technology, where the calibration significantly reduces bit-error-rates of a 72 GBit/s (8 GBit/s per lane) link over 4 mm on-chip interconnect. DOI: 10.4018/jertcs.2012100103 International Journal of Embedded and Real-Time Communication Systems, 3(4), 42-56, October-December 2012 43 Copyright © 2012, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited. (Winter et al., 2010), where higher layer pointto-point links bridge distances over multiple cores. As link data rates increase, the influence of process variations gets more severe especially in sub-100nm CMOS technologies. To achieve high data rates and maximize yield, calibration techniques have to be employed to compensate static mismatch variations. In Höppner et al. (2010) a calibration strategy with optimal sizing of compensation delay elements has been proposed. However, measurement access to on-chip signal characteristics is required. Asynchronous sub-sampling, where a high-speed signal is periodically sampled by a low-speed clock, is widely used for on-chip measurement purposes. In Schaub et al. (2008) on-chip oscilloscopes using asynchronous sampling clocks are presented which allow measurement of highspeed signals but require low jitter sampling clocks. This is a major drawback for complex MPSoCs where measurement signals have to be distributed over longer distances with negligible circuit and area overhead. In Amrutur et al. (2010) measurement of static skews of periodic signals is proposed using statistical averaging. This approach eases integration due to relaxed requirements for sample clock quality. Using this method periodic on-chip signals whose period is in the range of sample clock jitter can be characterized. This work presents an asynchronous subsampling technique (Höppner et al., 2011) to provide measurement access to delay characteristics of multiple high-speed NoC links in a 65 nm MPSoC. Therefore, a low frequency asynchronous sampling clock with relaxed jitter requirements can be used which simplifies integration and scalability. NOC LINK ARCHITECTURE","PeriodicalId":359507,"journal":{"name":"Int. J. Embed. Real Time Commun. Syst.","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127374805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Classes of Attacks for Tactical Software Defined Radios","authors":"Fabrício Alves Barbosa da Silva, D. Moura, J. F. Galdino","doi":"10.4018/jertcs.2012100104","DOIUrl":"https://doi.org/10.4018/jertcs.2012100104","url":null,"abstract":"This survey presents a classification of attacks that Software Communications Architecture (SCA) compliant Software Defined Radios (SDR) can suffer. This paper also discusses how attack mitigation strategies can impact the development of a SCA-compliant software infrastructure and identifies several research directions related to SDR security. The SCA standard was originally proposed by the Joint Tactical Radio System program (JTRS), which is a program for the development of military tactical radios sponsored by the US Department of Defense. The classification presented in this paper is based on attack results on the radio set, which can also be associated with the adversary’s objectives when planning an intrusion. The identification of classes of attacks on a radio, along with the associated threats and vulnerabilities, is the first step in engineering a secure SDR system. It precedes the identification of security requirements and the development of security mechanisms. Therefore, the identification of classes of attacks is a necessary step for the definition of realistic and relevant security requirements.","PeriodicalId":359507,"journal":{"name":"Int. J. Embed. Real Time Commun. Syst.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117280789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Simulation Tool for Real-Time Hybrid-Cooperative Positioning Algorithms","authors":"F. Sottile, Mauricio A. Caceres, M. Spirito","doi":"10.4018/jertcs.2012070105","DOIUrl":"https://doi.org/10.4018/jertcs.2012070105","url":null,"abstract":"The authors propose a simulation tool ST able to test real-time hybrid GNSS/terrestrial and cooperative positioning algorithms that fuse both pseudorange measurements from satellites and terrestrial range measurements based on radio frequency communication performed between nodes of a wireless network. In particular, the ST simulates devices belonging to a peer-to-peer P2P wireless network where peers, equipped also with a GNSS receiver, cooperate among them by exchanging aiding data in order to improve both positioning accuracy and availability. Furthermore, the authors propose a method to increase the robustness of cooperative algorithms based on the estimated position covariance matrix. In particular, the proposed approach assures a faster estimation convergence and improved accuracy while lowering computational complexity and network traffic. Finally, the authors tested the sensitivity of the implemented positioning algorithms through the ST in two different scenarios, first in presence of high level of pseudorange noise and then in presence of a malicious peer in the P2P network.","PeriodicalId":359507,"journal":{"name":"Int. J. Embed. Real Time Commun. Syst.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114456274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recent Trends in Interference Mitigation and Spoofing Detection","authors":"F. Dovis, L. Musumeci, N. Linty, M. Pini","doi":"10.4018/jertcs.2012070101","DOIUrl":"https://doi.org/10.4018/jertcs.2012070101","url":null,"abstract":"This paper gives a classification of intentional and unintentional threats, such as interference, jamming and spoofing, and discusses some of the recent trends concerning techniques for their detection and mitigation. Despite the fact that these phenomena have been studied since the early stages of Global Positioning System GPS, they were mainly addressed for military applications of Global Navigation Satellite Systems GNSS. However, a wide range of recent civil applications related to user's safety or featuring financial implications would be deeply affected by interfering or spoofing signals intentionally created. For such a reason, added value processing algorithms are being studied and designed, in order to improve accuracy and robustness of the receiver and to assure the reliability of the estimated position and time solution.","PeriodicalId":359507,"journal":{"name":"Int. J. Embed. Real Time Commun. Syst.","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127525078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}