On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links

This paper presents techniques for measurement and compensation of timing variations in clock and data channels of source-synchronous high-speed serial network-on-chip (NoC) links. Timing mismatch measurements are performed by means of asynchronous sub-sampling. This allows the use of low quality sampling clocks to reduce test hardware overhead for integration into complex MPSoCs (Multiprocessor System-on-Chip) with multiple NoC links. The effect of clock jitter on the measurement results is evaluated. Delay mismatch is compensated by tunable delay cells. The proposed technique enables compensation of delay variations to realize high-speed NoC links with sufficient yield. It is demonstrated at NoC links as part of an MPSoC in 65 nm Complementary Metal Oxide Semiconductor technology, where the calibration significantly reduces bit-error-rates of a 72 GBit/s (8 GBit/s per lane) link over 4 mm on-chip interconnect. DOI: 10.4018/jertcs.2012100103 International Journal of Embedded and Real-Time Communication Systems, 3(4), 42-56, October-December 2012 43 Copyright © 2012, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited. (Winter et al., 2010), where higher layer pointto-point links bridge distances over multiple cores. As link data rates increase, the influence of process variations gets more severe especially in sub-100nm CMOS technologies. To achieve high data rates and maximize yield, calibration techniques have to be employed to compensate static mismatch variations. In Höppner et al. (2010) a calibration strategy with optimal sizing of compensation delay elements has been proposed. However, measurement access to on-chip signal characteristics is required. Asynchronous sub-sampling, where a high-speed signal is periodically sampled by a low-speed clock, is widely used for on-chip measurement purposes. In Schaub et al. (2008) on-chip oscilloscopes using asynchronous sampling clocks are presented which allow measurement of highspeed signals but require low jitter sampling clocks. This is a major drawback for complex MPSoCs where measurement signals have to be distributed over longer distances with negligible circuit and area overhead. In Amrutur et al. (2010) measurement of static skews of periodic signals is proposed using statistical averaging. This approach eases integration due to relaxed requirements for sample clock quality. Using this method periodic on-chip signals whose period is in the range of sample clock jitter can be characterized. This work presents an asynchronous subsampling technique (Höppner et al., 2011) to provide measurement access to delay characteristics of multiple high-speed NoC links in a 65 nm MPSoC. Therefore, a low frequency asynchronous sampling clock with relaxed jitter requirements can be used which simplifies integration and scalability. NOC LINK ARCHITECTURE