{"title":"Generalized fractal-wavelet transforms for image representation and compression","authors":"E. Vrscay, F. Mendivil","doi":"10.1109/CCECE.1997.608265","DOIUrl":"https://doi.org/10.1109/CCECE.1997.608265","url":null,"abstract":"In this paper a set of generalized 2D fractal-wavelet transforms is introduced. Their primary difference from the usual transforms lies in treating \"horizontal\", \"vertical\" and \"diagonal\" quadtrees independently. Although more parameters are required, the added flexibility makes it quite tractable for image compression. Even the possibility of independent scaling factors but common parent blocks for the three sets of quadtrees gives excellent approximations with quite high compression ratios.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116262648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hybrid permutation frequency phase modulation","authors":"A. Yongaçoğlu, Wensheng Li","doi":"10.1109/CCECE.1997.614824","DOIUrl":"https://doi.org/10.1109/CCECE.1997.614824","url":null,"abstract":"In mobile radio and satellite communications, power and bandwidth efficient modulation schemes are highly desirable, For this purpose, we propose a new modulation technique called hybrid permutation frequency phase modulation (HPM). The performance of HPM has been studied in AWGN and frequency selective Rayleigh fading channels. Coded HPM is proposed for achieving diversity transmission over fading channels.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123376647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault detection and fault related performance degradation in sonar arrays","authors":"N.T. Allcott","doi":"10.1109/CCECE.1997.608299","DOIUrl":"https://doi.org/10.1109/CCECE.1997.608299","url":null,"abstract":"It is desirable to maximize sonar gain against noise and interference in the prevailing underwater acoustic environment. Although significant emphasis is placed upon monitoring and modeling underwater acoustics for these purposes, little attention is paid to sensing the prevailing sonar configuration, especially deficiencies in the configuration arising from faults, design conditions, or improper operation. Yet, these deficiencies can degrade sonar performance as seriously as external environmental factors. Several techniques are examined for detecting fault related sonar configuration deficiencies and evaluating their effect on sonar performance. In particular, these analysis techniques are employed within a hierarchical framework that specifies the fault detection and performance evaluation methodology. The usefulness of this approach is demonstrated using both simulated data examples and real data gathered from towed array trials at sea.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123695147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Nondeterministic automata as discrete approximations for continuous and hybrid systems-an approach to hybrid control systems design","authors":"J. Raisch, S. O'Young, C. Meder","doi":"10.1109/CCECE.1997.614810","DOIUrl":"https://doi.org/10.1109/CCECE.1997.614810","url":null,"abstract":"The contribution addresses the problem of approximating continuous or hybrid plant models by nondeterministic automata. The accuracy of the discrete approximation can be adjusted to reflect various design specifications. The behaviour of the underlying continuous (or hybrid) system is covered by the behaviour of its discrete approximation. Hence, a supervisory control scheme which forces an approximating automaton to meet a given set of specifications will also make the continuous (hybrid) \"base\" system obey the specifications.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123014552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hysteresis current controlled PWM converter for AC/AC voltage control","authors":"M. A. Choudhury, K. Rahman, M. Rahman, A. Bhuiya","doi":"10.1109/CCECE.1997.608250","DOIUrl":"https://doi.org/10.1109/CCECE.1997.608250","url":null,"abstract":"Current controlled strategies can be adopted in pulse width modulated (PWM) AC-AC power converters to regulate the load current having ripples within a band. Hysteresis current control techniques are widely used in high performance AC-DC-AC power converter fed drives. In this paper, a novel hysteresis current controller for an AC-AC buck power converter with regulated load current is presented. Two topologies of the proposed controller and converter in four quadrant and two quadrant modes of operation are analyzed. Sample controllers for both the topologies are simulated and realized. Details of simulation and practical controller implementation with integrated circuits are given. The proposed schemes have been found to offer high performance and are suitable for applications of all power levels.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"129 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124243165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A modified BPTT algorithm for trajectory learning in block-diagonal recurrent neural networks","authors":"S. Sivakumar, W. Robertson, W. Phillips","doi":"10.1109/CCECE.1997.614848","DOIUrl":"https://doi.org/10.1109/CCECE.1997.614848","url":null,"abstract":"This paper deals with a discrete time recurrent neural network (DTRNN) with a block-diagonal feedback weight matrix, called the block-diagonal recurrent neural network (BDRNN), that allows a simplified approach to online trajectory learning. The BDRNN is a sparse but structured architecture in which the feedback connections are restricted to between pairs of state variables. The block-diagonal structure of the BDRNN is exploited to modify the backpropagation-through-time (BPTT) algorithm to reduce the storage requirements while still maintaining exactness and locality of gradient computation. To achieve this, a numerically stable method for recomputing the state variables in the backward pass of the BPTT algorithm is presented.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126310062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Pipelined digital design in SRAM FPGAs","authors":"H. Ho, V. Szwarc, T. Kwasniewski","doi":"10.1109/CCECE.1997.614780","DOIUrl":"https://doi.org/10.1109/CCECE.1997.614780","url":null,"abstract":"Pipelined architectures have been successfully used in both gate array and standard cell technology to augment the throughput of arithmetic and DSP circuitry. The effectiveness of pipelining in SRAM FPGAs depends upon the architecture and routing characteristics of the device technology as well as the actual circuit implementation. The design and performance of a 24 bit ripple adder, an 8/spl times/9 bit array multiplier, and a 4 tap FIR filter are presented in this paper. The circuit designs implemented in AT&T's ORCA devices are considered with and without pipelining.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129939173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new generalized direct frequency converter","authors":"S. H. Hosseini, M. Yari, J. Senthil, R. Mathur","doi":"10.1109/CCECE.1997.608248","DOIUrl":"https://doi.org/10.1109/CCECE.1997.608248","url":null,"abstract":"In this paper, the authors introduce a new direct frequency converter topology in which, by using the standard three-phase voltage waveform at the input, three-phase sinusoidal outputs of any desired frequency and amplitude can be generated. The harmonic content of output voltage is significantly less than other classical cycloconverters. It is illustrated that even under unbalanced and highly distorted input voltage waveforms, the output waveform turns but to be reasonably clean and balanced. In light of such good performance, the authors conclude that this new generalized direct frequency converter (GDFC) can be effectively applied as a controlled power source for AC or DC motor drives as well as an active filter.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131351197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Prototyping from SDL specifications using a real-time concurrent logic language","authors":"R. Kovacevic, D. Prairie, P. Dasiewicz","doi":"10.1109/CCECE.1997.614840","DOIUrl":"https://doi.org/10.1109/CCECE.1997.614840","url":null,"abstract":"The ITU specification and description language (SDL) is often used in the field of telecommunications to specify both protocols and overall systems. Since such systems are often both large and complex, it is desirable to simulate and execute SDL. Although traditional programming languages such as C and Pascal are adequate for implementing such a simulator/code generator, several advantages can be gained from using a real time logic language. Real-Time Parlog presents many advantages since it directly supports both the concepts of timing and concurrency, without direct user knowledge of the underlying operating system.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125620323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Asynchronous design in dynamic CMOS","authors":"J. Ahmed, S. Zaky","doi":"10.1109/CCECE.1997.608275","DOIUrl":"https://doi.org/10.1109/CCECE.1997.608275","url":null,"abstract":"The design for dynamic CMOS cells that can be used as building blocks in an asynchronous pipeline are discussed in this paper. The proposed circuit elements are variations on TSPC logic using Sutherland's micropipeline structure combined with dual rail logic to detect operation completion. The resulting cell occupies more area than a TSPC cell, but has higher functionality because of the built-in data flow control mechanisms provided by the handshake signaling of the micropipeline structure.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121312315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}