Pipelined digital design in SRAM FPGAs

Pipelined architectures have been successfully used in both gate array and standard cell technology to augment the throughput of arithmetic and DSP circuitry. The effectiveness of pipelining in SRAM FPGAs depends upon the architecture and routing characteristics of the device technology as well as the actual circuit implementation. The design and performance of a 24 bit ripple adder, an 8/spl times/9 bit array multiplier, and a 4 tap FIR filter are presented in this paper. The circuit designs implemented in AT&T's ORCA devices are considered with and without pipelining.