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Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.最新文献

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A new BIST scheme for 5GHz low noise amplifiers 一种新的5GHz低噪声放大器的BIST方案
Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. Pub Date : 2004-05-23 DOI: 10.1109/ETSYM.2004.1347625
J. Ryu, Bruce C. Kim, I. Sylla
{"title":"A new BIST scheme for 5GHz low noise amplifiers","authors":"J. Ryu, Bruce C. Kim, I. Sylla","doi":"10.1109/ETSYM.2004.1347625","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347625","url":null,"abstract":"This paper presents a new low-cost Built-In Self-Test (BIST) circuit for measuring gain, noise figure and input impedance of 5GHz low noise amplifier (LNA). The BIST circuit is designed using 0.18 µm SiGe technology. The test technique utilizes input impedance matching and output transient voltage measurements. The technique is simple and inexpensive.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115203409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
All-pass SC biquad reconfiguration scheme for oscillation based analog BIST 基于振荡的模拟BIST全通SC双组重构方案
Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. Pub Date : 2004-05-23 DOI: 10.1109/ETSYM.2004.1347626
U. Kac, F. Novak
{"title":"All-pass SC biquad reconfiguration scheme for oscillation based analog BIST","authors":"U. Kac, F. Novak","doi":"10.1109/ETSYM.2004.1347626","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347626","url":null,"abstract":"In this work, a test reconfiguration scheme for switched-capacitor stages featuring biquadratic transfer functions with finite complex zeros is presented. The proposed approach allows to perform the oscillation-based test of relevant biquad parameters without the need for complex stimulus generation or analog output processing and requires low analog area overhead. The scheme is especially suitable for implementing low-cost analog BIST of SC filter cores embedded within complex mixed-signal devices.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131901044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution 嵌入式sram的动态读破坏故障分析与测试解决方案
Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. Pub Date : 2004-05-23 DOI: 10.1109/ETSYM.2004.1347645
L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, Simone Borri, M. Bastian
{"title":"Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution","authors":"L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, Simone Borri, M. Bastian","doi":"10.1109/ETSYM.2004.1347645","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347645","url":null,"abstract":"This paper presents an analysis of dynamic faults in core-cell of SRAM memories. These faults are the consequence of resistive-open defects that appear more frequently in VDSM technologies. In particular, the study concentrates on those defects that generate dynamic Read Destructive Faults, dRDFs. In this paper, we demonstrate that read or write operations on a cell involve a stress on the other cells of the same word line. This stress, called Read Equivalent Stress (RES), has the same effect than a read operation. On this basis, we propose to modify the well known March C-, which does not detect dRDFs, into a new version able to detect them. This is obtained by changing its addressing order with the purpose of producing the maximal number of RES. This modification does not change the complexity of the algorithm and its capability to detect the former target faults.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133919479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 75
Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits 局部可靠性设计技术在降低CMOS组合逻辑电路损耗中的应用
Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. Pub Date : 2004-05-23 DOI: 10.1109/ETSYM.2004.1347593
Xiangdong Xuan, A. Chatterjee, A. Singh
{"title":"Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits","authors":"Xiangdong Xuan, A. Chatterjee, A. Singh","doi":"10.1109/ETSYM.2004.1347593","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347593","url":null,"abstract":"Based on reliability simulation and reliability hotspot identification with simulator ARET, a concept of local design-for-reliability is proposed and a detailed redesign algorithm has been developed for CMOS digital circuits under device degradation mechanisms, such as hot-carrier and gate oxide wear-out. This algorithm improves circuit overall reliability by modifying channel length of hotspot gate and channel widths of some other gates around hotspot iteratively. By performing local redesign for reliability, circuit reliability can be significantly improved, while the originally designed overall circuit performance is still maintained.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131788008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A design methodology to realize delay testable controllers using state transition information 一种利用状态转移信息实现延迟可测试控制器的设计方法
Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. Pub Date : 2004-05-23 DOI: 10.1109/ETSYM.2004.1347655
T. Iwagaki, S. Ohtake, H. Fujiwara
{"title":"A design methodology to realize delay testable controllers using state transition information","authors":"T. Iwagaki, S. Ohtake, H. Fujiwara","doi":"10.1109/ETSYM.2004.1347655","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347655","url":null,"abstract":"This paper proposes a non-scan design scheme to enhance delay fault testability of controllers. In this scheme, we utilize a given state transition graph (STG) to test delay faults in its synthesized controller. The original behavior of the STG is used during test application. For faults that cannot be detected by using the original behavior, we design an extra logic, called an invalid test state and transition generator, to make those faults detectable. Our scheme allows achieving short test application time and at-speed testing. We show the effectiveness of our method by experiments.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130796669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
User-constrained test architecture design for modular SOC testing 模块化SOC测试的用户约束测试架构设计
Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. Pub Date : 2004-05-23 DOI: 10.1109/ETSYM.2004.1347611
L. Krundel, S. Goel, E. Marinissen, M. Flottes, B. Rouzeyre
{"title":"User-constrained test architecture design for modular SOC testing","authors":"L. Krundel, S. Goel, E. Marinissen, M. Flottes, B. Rouzeyre","doi":"10.1109/ETSYM.2004.1347611","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347611","url":null,"abstract":"This paper discusses the extensions to the automatic SOC test architecture optimization tool TR-ARCHITECT that allow the user to partially specify the resulting test architecture. We describe a novel Test Architecture Specification (TAS) language, in which the user can express constraints with respect to (1) the number of Test Access Mechanisms (TAMs), (2) the TAM widths, (3) the assignment of modules to TAMs, and (4) the module ordering within a TAM. We also describe the extensions and modifications to the algorithms of TR-ARCHITECT that were necessary to incorporate the ability to satisfy the user constraints. We present experimental results for several ITC'02 SOC Test Benchmarks.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129896995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adder 一种利用码不相交和位重复加法器的自检乘法器
Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. Pub Date : 2004-05-23 DOI: 10.1109/ETSYM.2004.1347594
D. Marienfeld, E. Sogomonyan, V. Ocheretnij, M. Gössel
{"title":"A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adder","authors":"D. Marienfeld, E. Sogomonyan, V. Ocheretnij, M. Gössel","doi":"10.1109/ETSYM.2004.1347594","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347594","url":null,"abstract":"In this paper a new self-checking multiplier which consists of an AND-matrix, a carry-save adder and a final sumbit duplicated adder is proposed. The AND-matrix and the carry-save adder are parity checked. All errors due to single stuck-at faults in the combinational part and all even or odd (soft) errors in one of the duplicated output registers are detected. The parity checked carry-save adder is implemented by use of carry-dependent sum adder cells with a single carry-out signal. Compared to a corresponding multiplier without error detection the necessary area is about 125% to 135%.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128611349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage? 功能故障覆盖率:密室还是门级覆盖率的准确估计?
Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. Pub Date : 2004-05-23 DOI: 10.1109/ETSYM.2004.1347649
F. Fummi, C. Marconcini, G. Pravadelli
{"title":"Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage?","authors":"F. Fummi, C. Marconcini, G. Pravadelli","doi":"10.1109/ETSYM.2004.1347649","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347649","url":null,"abstract":"More and more functional verification is attracting EDA researchers and industrial companies interested in digital system validation. Coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck at fault model? The paper presents an accurate analysis of the correlation between the high-level bit coverage fault model and the gate-level stuck-at fault model.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129641563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Tests for address decoder delay faults in RAMs due to inter-gate opens 测试ram中由于门间打开导致的地址解码器延迟故障
Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. Pub Date : 2004-05-23 DOI: 10.1109/ETSYM.2004.1347646
A. V. Goor, S. Hamdioui, Z. Al-Ars
{"title":"Tests for address decoder delay faults in RAMs due to inter-gate opens","authors":"A. V. Goor, S. Hamdioui, Z. Al-Ars","doi":"10.1109/ETSYM.2004.1347646","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347646","url":null,"abstract":"This paper presents an electrical analysis of Address decoder Delay Faults 'AFDs' caused by resistive inter-gate opens in RAMs. It introduces a systematic method to explore the space of possible tests to detect these faults. The method is based on generating appropriate sensitizing address transitions and the corresponding sensitizing operation sequences.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126537073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Delay fault testing and silicon debug using scan chains 延迟故障测试和硅调试使用扫描链
Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. Pub Date : 2004-05-23 DOI: 10.1109/ETSYM.2004.1347600
R. Datta, A. Sebastine, J. Abraham
{"title":"Delay fault testing and silicon debug using scan chains","authors":"R. Datta, A. Sebastine, J. Abraham","doi":"10.1109/ETSYM.2004.1347600","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347600","url":null,"abstract":"This paper describes a novel technique to reuse the existing scanpaths in a chip for delay fault testing and silicon debug. Efficient test and debug techniques for VLSI chips are indispensable in Deep Submicron technologies. A systematic debug scheme is also necessary in order to reduce time-to-market. Due to stringent timing requirements of modern chips, test and debug schemes have to be tailored for detection and debug of functional defects as well as delay faults quickly and efficiently. The proposed technique facilitates an efficient scheme for detecting and debugging delay faults and has minimal area and power overhead.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133122031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
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