2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools最新文献_第7页

Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications 数据流应用的可组合动态电压和频率缩放和电源管理

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools Pub Date : 2010-09-01 DOI: 10.1109/DSD.2010.61

K. Goossens, Dongrui She, Aleksandar Milutinovic, A. Molnos

{"title":"Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications","authors":"K. Goossens, Dongrui She, Aleksandar Milutinovic, A. Molnos","doi":"10.1109/DSD.2010.61","DOIUrl":"https://doi.org/10.1109/DSD.2010.61","url":null,"abstract":"Composability means that the behaviour of an application, including its timing, is not affected by the absence or presence of other applications. It is required to be able to design, test, and verify applications independently. In this paper we define composable dynamic voltage and frequency scaling (DVFS) hardware, and composable power management. We ensure that the functional and temporal behaviours of an application are not affected by other applications, even when they are power managed. For dataflow applications with worst-case execution times per task, our power management is also predictable, i.e. guarantees end-to-end real-time requirements, even when the application is mapped on multiple processors that are power managed independently. Our method can be used with various DVFS architectures, such as on-chip and off-chip VF regulators. Our FPGA implementation models a system with multiple tiles, each containing a processor with local memory running a real-time operating system (RTOS) and power management. Tiles are interconnected by a network on chip, and communicate using shared memories. Experiments indicate energy savings of 68% w.r.t. no power management, and 40% w.r.t. power gating only. We also demonstrate composability and predictability on the platform in the presence of power management.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124937127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance 基于硬件的人脸识别实时性提升

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools Pub Date : 2010-09-01 DOI: 10.1109/DSD.2010.45

I. Sajid, Sotirios G. Ziavras, M. M. Ahmed

{"title":"Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance","authors":"I. Sajid, Sotirios G. Ziavras, M. M. Ahmed","doi":"10.1109/DSD.2010.45","DOIUrl":"https://doi.org/10.1109/DSD.2010.45","url":null,"abstract":"Real-time face recognition by computer systems is required in many commercial and security applications since it is the only way to protect privacy and security. On the other hand, face recognition generates huge amounts of data in real-time. Filtering out meaningful data from this raw data with high accuracy is a complex task. Most of the existing techniques primarily focus on the accuracy aspect using extensive matrix-oriented computations. Efficient realizations primarily reduce the computational space using eigenvalues. On the other hand, an eigenvalues oriented evaluation has minimum time complexity of O (n3), where n is the rank of the covariance matrix, the computation cost for co-variance generation is extra. Our frequency distribution curve (FDC) technique avoids matrix decomposition and other high computationally intensive matrix operations. FDC is formulated with a bias towards efficient hardware realization and high accuracy by using simple vector operations. FDC requires pattern vector (PV) extraction from an image within O (n2) time. Our enhanced FDC-based architecture proposed in this paper further shifts a computationally expensive component of FDC to the offline layer of the system, thus resulting in very fast online evaluation of the input data. Furthermore, efficient online testing is pursued as well using an adaptive controller (AC) for PV classification utilizing the Euclidian vector norm length. The pipelined AC architecture adapts to the availability of resources in the target silicon device. Our implementation on an XC5VSX50t FPGA demonstrates a high accuracy of 99% in face recognition for 400 images in the ORL database, generally requiring less than 200 nsec per image.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126184990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A New High-Level Methodology for Programming FPGA-Based Smart Camera 一种基于fpga的智能摄像机高级编程方法

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools Pub Date : 2010-09-01 DOI: 10.1109/DSD.2010.68

Nicolas Roudel, F. Berry, J. Sérot, L. Eck

引用次数: 6

Design of Trace-Based Split Array Caches for Embedded Applications 嵌入式应用中基于跟踪的分割阵列缓存设计

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools Pub Date : 2010-09-01 DOI: 10.1109/DSD.2010.33

A. Tokarnia, Marina Tachibana

{"title":"Design of Trace-Based Split Array Caches for Embedded Applications","authors":"A. Tokarnia, Marina Tachibana","doi":"10.1109/DSD.2010.33","DOIUrl":"https://doi.org/10.1109/DSD.2010.33","url":null,"abstract":"Since many embedded systems execute a predefined set of programs, tuning system components to application programs and data is the approach chosen by many design techniques to optimize performance and power consumption. In this paper, we propose a method based on the analysis of accesses to vector, arrays, and other complex data structures to design a size-constrained two-partition array cache. This method reorganizes the ways of set-associative arrays caches into partitions with different line sizes and defines array-partition mappings so as to minimize the average memory access energy-delay product. Experimental results have shown that these split array caches have lower average energy-delay product for memory accesses as compared with unified set-associative array caches of the same size. For an MPEG-2 decoder, even with no parallel accesses to cache partitions, the average memory access energy-delay product of an 8K-byte trace-based split array cache is reduced by 50% as compared to that of the unified set-associative array cache with the lowest energy-delay product. If 25% of the accesses occur in pairs, there is an additional reduction of 9%.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128021811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

ALOE-Based Flexible LDPC Decoder 基于芦荟的柔性LDPC解码器

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools Pub Date : 2010-09-01 DOI: 10.1109/DSD.2010.107

Ismael Gómez Miguelez, Massimo Camatel, J. Bracke, V. Marojevic, A. Gelonch, F. Vacca, G. Masera

引用次数: 0

Design Methodology for a High Performance Robust DVB-S2 Decoder Implementation 一种高性能稳健DVB-S2解码器实现的设计方法

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools Pub Date : 2010-09-01 DOI: 10.1109/DSD.2010.40

F. Berthelot, François Charot, Charles Wagner, C. Wolinski

引用次数: 1

A Class of Recursive Networks on a Chip for Enhancing Intercluster Parallelism 一类增强集群间并行性的芯片递归网络

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools Pub Date : 2010-09-01 DOI: 10.1109/DSD.2010.46

Masaru Takesue

引用次数: 0

Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application 低功耗90nm查找表(LUT)性能分析

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools Pub Date : 2010-09-01 DOI: 10.1109/DSD.2010.72

Deepak Kumar, Pankaj Kumar, M. Pattanaik

引用次数: 16

System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes 超低功耗无线传感器节点的系统级综合

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools Pub Date : 2010-09-01 DOI: 10.1109/DSD.2010.88

Muhammad Adeel Pasha, Steven Derrien, O. Sentieys

引用次数: 12

A Packet Classifier Using a Parallel Branching Program Machine 使用并行分支程序机的包分类器

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools Pub Date : 2010-09-01 DOI: 10.1109/DSD.2010.18

Hiroki Nakahara, Tsutomu Sasao, M. Matsuura

引用次数: 11