Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001最新文献_第3页

Worst cases for correct rounding of the elementary functions in double precision 在双精度中正确舍入初等函数的最坏情况

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930110

V. Lefèvre, J. Muller

引用次数: 83

On-line arithmetic for detection in digital communication receivers 数字通信接收机中的在线检测算法

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930127

S. Rajagopal, Joseph R. Cavallaro

{"title":"On-line arithmetic for detection in digital communication receivers","authors":"S. Rajagopal, Joseph R. Cavallaro","doi":"10.1109/ARITH.2001.930127","DOIUrl":"https://doi.org/10.1109/ARITH.2001.930127","url":null,"abstract":"This paper demonstrates the advantages of using online arithmetic for traditional and advanced detection algorithms for communication systems. Detection is one of the core computationally-intensive physical layer operations in a communication receiver and determines the communication data rates. Detection algorithms typically involve hard decisions (sign based testing) to find the sign of the transmitted information bit. This results in extraneous computations in a conventional number system as the sign is obtained only at the end due to the least significant digit first (LSDF) nature of computations. Online arithmetic, based on a signed digit number representation, provides most significant digit first (MSDF) computation. Hence, the computations can stop after the first non-zero MSD (sign) is computed and additional computations for the successive digits can be avoided. Back-conversion to a conventional number system is not required as the sign of the digit represents the detected bit. A comparison of a radix-4 serial digit on-line multiuser detector with an 8-bit parallel conventional arithmetic multiuser detector shows a decrease in latency by 1.79X, a 3X increase in throughput, and possible savings in area.","PeriodicalId":356830,"journal":{"name":"Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134591095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

In order issue out-of-order execution floating-point coprocessor for CalmRISC32 CalmRISC32的顺序问题乱序执行浮点协处理器

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930119

C. Jeong, W. Park, T. Han, M. Lee, Sang-Woo Kim

引用次数: 6

Analysis of column compression multipliers 列压缩乘法器分析

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930101

K'Andrea C. Bickerstaff, E. Swartzlander, M. Schulte

引用次数: 89

Some improvements on multipartite table methods 多部表方法的一些改进

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930112

F. D. Dinechin, A. Tisserand

引用次数: 72

Improved table lookup algorithms for postscaled division 改进后尺度除法的表查找算法

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930109

D. Matula

{"title":"Improved table lookup algorithms for postscaled division","authors":"D. Matula","doi":"10.1109/ARITH.2001.930109","DOIUrl":"https://doi.org/10.1109/ARITH.2001.930109","url":null,"abstract":"Postscaled division is a non-iterative algorithm delivering a quotient of single precision accuracy by the three term product (xy/spl circ/)c and of double precision accuracy by the formula [(xy/spl circ/)c][2-(yy/spl circ/)c]. Here x is the dividend, y/spl circ/ is a low order part complemented form of the divisor y, and c is a table lookup value approximating a \"reciprocal function\" 1/(yy/spl circ/) to a precision of over 27 bits. Table lookup latency is hidden by performing the lookup in parallel with the first multiplication (xy/spl circ/), with the second multiplication the \"postscaling\" by the lookup function value. Our contribution is the description of two new lookup algorithms for approximating the reciprocal function 1/yy/spl circ/ to high accuracy in fewer cycles than a typical floating point multiply latency. Our indirect bipartite lookup procedure has a latency of two successive lookups followed by a small integer addition. This first algorithm generates a 27 bit approximation of 1/yy/spl circ/ with total table size about 5 Kbytes. Our second lookup algorithm generates a 34 bit approximation with latency determined by 11 and 12 bit table lookups and a 4-1 addition. This second approximation employs some 20 Kbytes of tables to allow for a double extended precision division result in the same number of cycles as a double precision result.","PeriodicalId":356830,"journal":{"name":"Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134024377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

A hardware algorithm for computing reciprocal square root 计算倒数平方根的硬件算法

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930108

N. Takagi

引用次数: 15

On the design of fast IEEE floating-point adders 快速IEEE浮点加法器的设计

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930118

P. Seidel, G. Even

{"title":"On the design of fast IEEE floating-point adders","authors":"P. Seidel, G. Even","doi":"10.1109/ARITH.2001.930118","DOIUrl":"https://doi.org/10.1109/ARITH.2001.930118","url":null,"abstract":"We present an IEEE floating-point adder (FP-adder) design. The adder accepts normalized numbers, supports all four IEEE rounding modes, and outputs the correctly normalized rounded sum/difference in the format required by the IEEE standard. The latency of the design for double precision is roughly 24 logic levels, not including delays of latches between pipeline stages. Moreover, the design can be easily partitioned into 2 stages consisting of 12 logic levels each, and hence, can be used with clock periods that allow for 12 logic levels between latches. The FP-adder design achieves low latency by combining various optimization techniques such as: a non-standard separation into two paths, a simple rounding algorithm, unifying rounding cases for addition and subtraction, sign-magnitude computation of a difference based on complement subtraction, compound adders, and fast circuits for approximate counting of leading zeros from borrow-save representation. A comparison of our design with other implementations suggests a reduction in the latency by at least two logic levels as well as simplified rounding implementation. A reduced precision version of our algorithm has been verified by exhaustive testing.","PeriodicalId":356830,"journal":{"name":"Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134620739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 43

Bounds on runs of zeros and ones for algebraic functions 代数函数的0和1的边界

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930099

T. Lang, J. Muller

引用次数: 28

Algorithms for quad-double precision floating point arithmetic 四双精度浮点运算算法

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2000-10-30 DOI: 10.1109/ARITH.2001.930115

Yozo Hida, X. Li, D. Bailey

引用次数: 274