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Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001最新文献

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Optimised squaring of long integers using precomputed partial products 使用预先计算的部分积优化长整数的平方
Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930106
B. Phillips
{"title":"Optimised squaring of long integers using precomputed partial products","authors":"B. Phillips","doi":"10.1109/ARITH.2001.930106","DOIUrl":"https://doi.org/10.1109/ARITH.2001.930106","url":null,"abstract":"This paper considers the combination of two familiar, but hitherto incompatible, arithmetic techniques: optimised squaring and precomputing partial products. Optimised squaring reduces the total accumulation effort required for squaring when compared with multiplication, by removing repeated digit products from the accumulation tree. Iterative implementations of integer multiplication, in which each partial product is evaluated and accumulated in turn, can often be accelerated by precomputing the set of partial products and accumulating these as required. Iterative implementations of optimised squaring cannot benefit from the same straightforward technique. A new algorithm for optimised squaring is developed which reconciles the these two techniques and which is an improvement over squaring by multiplication for some platforms. The result is of significance for the implementation of public key cryptography on smart cards or other small footprint devices.","PeriodicalId":356830,"journal":{"name":"Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127387629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Parallel prefix adder design 并行前缀加法器设计
Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930122
A. Beaumont-Smith, C. Lim
{"title":"Parallel prefix adder design","authors":"A. Beaumont-Smith, C. Lim","doi":"10.1109/ARITH.2001.930122","DOIUrl":"https://doi.org/10.1109/ARITH.2001.930122","url":null,"abstract":"The paper introduces two innovations in the design of prefix adder carry trees: use of high-valency prefix cells to achieve low logical depth and end-around carry adders with reduced fan-out loading (compared with the carry select and flagged prefix adders). An algorithm for generating parallel prefix carry trees suitable for use in a VLSI synthesis tool is presented with variable parameters including carry tree width, prefix cell valency, and the spacing of repeated carry trees. The area-delay design space is mapped for a 0.25 /spl mu/m CMOS technology for a range of adder widths as a comparative study.","PeriodicalId":356830,"journal":{"name":"Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114227663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 125
A decimal floating-point specification 十进制浮点数规范
Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930114
M. Cowlishaw, E. Schwarz, Ronald M. Smith, C. Webb
{"title":"A decimal floating-point specification","authors":"M. Cowlishaw, E. Schwarz, Ronald M. Smith, C. Webb","doi":"10.1109/ARITH.2001.930114","DOIUrl":"https://doi.org/10.1109/ARITH.2001.930114","url":null,"abstract":"Even though decimal arithmetic is pervasive in financial and commercial transactions, computers are still implementing almost all arithmetic calculations using binary arithmetic. As chip real estate becomes cheaper it is becoming likely that more computer manufacturers will provide processors with decimal arithmetic engines. Programming languages and databases are expanding the decimal data types available while there has been little change in the base hardware. As a result, each language and application is defining a different arithmetic and few have considered the efficiency of hardware implementations when setting requirements. We propose a decimal format which meets the requirements of existing standards for decimal arithmetic and is efficient for hardware implementation. We propose this specification in the hope that designers will consider providing decimal arithmetic in future microprocessors and that future decimal software specifications will consider hardware efficiencies.","PeriodicalId":356830,"journal":{"name":"Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001","volume":"281 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131558635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
Generation and analysis of hard to round cases for binary floating point division 二进制浮点除法难以舍入的生成与分析
Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930111
L. McFearin, D. Matula
{"title":"Generation and analysis of hard to round cases for binary floating point division","authors":"L. McFearin, D. Matula","doi":"10.1109/ARITH.2001.930111","DOIUrl":"https://doi.org/10.1109/ARITH.2001.930111","url":null,"abstract":"We investigate two sets of hard to round p/spl times/p bit fractions arising from division of a normalized p bit floating point dividend by a normalized p bit floating point divisor. These sets are characterized by the p/spl times/p bit fraction's quotient bit string, beginning with or just after the round bit, having the maximum number (p-1) of repeating like bits, specifically 00...01 or 11...10 for the directed rounding \"RD-hard\" set and 100...01 or 11...10 for the round-to-nearest \"RN/sub -/hard\" set. We show both the p/spl times/p bit RD-hard and RN-hard sets to be of size at least 2/sup p-2/ and at most 2/sup p-1/. Two dimensional quotient vs. divisor plots empirically reveal both the RD-hard and RN-hard sets of p/spl times/p bit fractions to be jointly widely distributed. Analysis of patterns and linear sequences of fractions visible in the quotient vs. divisor plots leads to simplified procedures for generating test suites of hard to round fractions. Our strongest computational result is the derivation of formulas that allow 2/sup (p/2)+O(1)/ RD-hard and RN-hard p/spl times/p bit fractions to be enumerated based on sequential incrementation of respective numerators and denominators.","PeriodicalId":356830,"journal":{"name":"Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126339453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Efficient computation of multiplicative inverses for cryptographic applications 密码应用中乘法逆的高效计算
Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930105
M. A. Hasan
{"title":"Efficient computation of multiplicative inverses for cryptographic applications","authors":"M. A. Hasan","doi":"10.1109/ARITH.2001.930105","DOIUrl":"https://doi.org/10.1109/ARITH.2001.930105","url":null,"abstract":"Among the basic arithmetic operations over finite fields, the computation of a multiplicative inverse is the most time consuming operation. A number of methods are presented to efficiently compute the inverse using the extended Euclidean algorithm. The proposed methods can significantly reduce the computation time over large fields where the field elements are represented using a multi-precision format. A hardware structure for the inverter is also presented. The structure is area efficient and is suitable for resource constrained systems. Additionally, an application of the proposed inversion algorithm is given in the context of elliptic curve cryptography.","PeriodicalId":356830,"journal":{"name":"Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132802209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
High-performance architectures for elementary function generation 用于初级函数生成的高性能架构
Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930113
Jun Cao, Belle W. Y. Wei, Jie Cheng
{"title":"High-performance architectures for elementary function generation","authors":"Jun Cao, Belle W. Y. Wei, Jie Cheng","doi":"10.1109/ARITH.2001.930113","DOIUrl":"https://doi.org/10.1109/ARITH.2001.930113","url":null,"abstract":"High-speed elementary function generation is crucial to the performance of many DSP applications. This paper presents three new architectures for generating elementary functions with IEEE single precision using second-order interpolation. These designs have been developed through a combination of architectural innovations and algorithm developments. They represent a range of trade-off between the use of memory modules and computational circuits. Our most memory intensive architecture uses one third less memory than alternative schemes while incurring no time penalty and minimal additional circuitry.","PeriodicalId":356830,"journal":{"name":"Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001","volume":"73 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123542315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 70
Leading zero anticipation and detection-a comparison of methods 前导零预判与检测——方法的比较
Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930098
M. Schmookler, K. Nowka
{"title":"Leading zero anticipation and detection-a comparison of methods","authors":"M. Schmookler, K. Nowka","doi":"10.1109/ARITH.2001.930098","DOIUrl":"https://doi.org/10.1109/ARITH.2001.930098","url":null,"abstract":"Design of the leading zero anticipator (LZA) or detector (LZD) is pivotal to the normalization of results for addition and fused multiplication-addition in high-performance floating point processors. This paper formalizes the analysis and describes some alternative organizations and implementations from the known art. It shows how choices made in the design are often dependent on the overall design of the addition unit, on how subtraction is handled when the exponents are the same, and on how it detects and corrects for the possible one-bit error of the LZA.","PeriodicalId":356830,"journal":{"name":"Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126536664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 128
Binary multiplication radix-32 and radix-256 二进制乘法基数32和基数256
Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930100
P. Seidel, L. McFearin, D. Matula
{"title":"Binary multiplication radix-32 and radix-256","authors":"P. Seidel, L. McFearin, D. Matula","doi":"10.1109/ARITH.2001.930100","DOIUrl":"https://doi.org/10.1109/ARITH.2001.930100","url":null,"abstract":"Multipliers are used at many different places in microprocessor design. As the non-memory sub-blocks of the microprocessor with the largest size and delay, multipliers have a big impact on the cycle time of the microprocessor. Targeting deeper pipelines and higher clock frequencies, there is a growing demand for multiplier designs that can be split into shorter stages. For this purpose, the use of Booth recoding has been a popular method to cut down the number of partial products in a multiplier to reduce the delay of the partial product accumulation and to simplify the partition of the multiplier into several shorter stages. The complexity to pre-compute an increasing number of digit multiples of the multiplicand within the multiplier unit limits the use of Booth recoding mainly to radices 4 and 8. We propose novel encoding schemes for the implementation of higher radix multiplication. In particular we consider multiplication radix-32 and radix-256. The features provide more flexible multiplier designs that can be implemented in shorter pipeline stages. We compare the proposed designs with multipliers that use traditional Booth recoding.","PeriodicalId":356830,"journal":{"name":"Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116915399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Unrestricted faithful rounding is good enough for some LNS applications 不受限制的忠实舍入对于某些LNS应用来说已经足够好了
Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930125
M. Arnold, C. D. Walter
{"title":"Unrestricted faithful rounding is good enough for some LNS applications","authors":"M. Arnold, C. D. Walter","doi":"10.1109/ARITH.2001.930125","DOIUrl":"https://doi.org/10.1109/ARITH.2001.930125","url":null,"abstract":"We propose to relax the restricted form of faithful rounding used in prior 32 bit logarithmic number system (LNS) implementations. Unrestricted faithful rounding yields three- to six-fold savings in VLSI ROM size (or four- to six-fold savings in FPGA table size) with only a modest increase in error. This can be acceptable for the DSP and multimedia applications in which the non-standard LNS is a candidate for adoption. Such applications are cost sensitive, and the tremendous cost reduction of the LNS model proposed should argue very favourably for its adoption.","PeriodicalId":356830,"journal":{"name":"Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129442304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
Faithful powering computation using table look-up and a fused accumulation tree 使用表查找和融合积累树忠实地进行计算
Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930102
José-Alejandro Piñeiro, J. Bruguera, J. Muller
{"title":"Faithful powering computation using table look-up and a fused accumulation tree","authors":"José-Alejandro Piñeiro, J. Bruguera, J. Muller","doi":"10.1109/ARITH.2001.930102","DOIUrl":"https://doi.org/10.1109/ARITH.2001.930102","url":null,"abstract":"A method for the calculation of faithfully rounded single-precision floating-point powering (X/sup p/) is proposed in this paper. This method employs table look-up and a second-degree minimax approximation, which allows the employment of reduced size tables to store the coefficients from the polynomial approximation. A specialized squaring unit and a fused accumulation tree carry out with the computation of the quadratic polynomial. Both unfolded and pipelined architectures are presented, and the results of a pre-layout synthesis performed using CMOS 0.35 /spl mu/m technology are shown, achieving a 50% area reduction from linear approximation methods, and with improved speed over other second-degree approximation based algorithms. The pipelined architecture has a latency of three cycles and a throughput of one result per cycle.","PeriodicalId":356830,"journal":{"name":"Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001","volume":"37 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128659834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 86
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