Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001最新文献

Using the reverse-carry approach for double datapath floating-point addition 使用反向进位方法进行双数据路径浮点加法

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930120

J. Bruguera, T. Lang

引用次数: 8

Modular multiplication and base extensions in residue number systems 余数系统中的模乘法与基扩展

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930104

J. Bajard, Laurent-Stéphane Didier, Peter Kornerup

引用次数: 118

Low-power properties of the logarithmic number system 对数数制的低功耗特性

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930124

Vassilis Paliouras, T. Stouraitis

引用次数: 81

Effective continued fractions 有效连分数

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930116

D. Lester

引用次数: 17

The use of the multi-dimensional logarithmic number system in DSP applications 多维对数系统在DSP中的应用

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930126

V. Dimitrov, J. Eskritt, L. Imbert, G. Jullien, W. Miller

引用次数: 26

Correctly rounded reciprocal square-root by digit recurrence and radix-4 implementation 正确四舍五入倒数平方根的数字递归和根号4的实现

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930107

T. Lang, E. Antelo

引用次数: 4

A design of radix-2 on-line division using LSA organization 基于LSA组织的基数-2在线除法设计

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930128

A. Tenca, Safiullah Hussaini

引用次数: 5

High speed parallel-prefix modulo 2/sup n/+1 adders for diminished-one operands 高速并行前缀模2/sup n/+1加法器的减少- 1操作数

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930121

H. T. Vergos, D. Nikolos, C. Efstathiou

引用次数: 11

1 GHz HAL SPARC64/sup R/ Dual Floating Point Unit with RAS features 1 GHz HAL SPARC64/sup R/双浮点单元具有RAS功能

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930117

A. Naini, Atul Dhablania, Warren James, Debjit Das Sarma

{"title":"1 GHz HAL SPARC64/sup R/ Dual Floating Point Unit with RAS features","authors":"A. Naini, Atul Dhablania, Warren James, Debjit Das Sarma","doi":"10.1109/ARITH.2001.930117","DOIUrl":"https://doi.org/10.1109/ARITH.2001.930117","url":null,"abstract":"An IEEE compliant, 1 GHz Sparc64-V Floating-Point Unit (FPU) with reliability-accessibility-serviceability (RAS) features and partial support for denormal operands and results is presented. The FPU has two functional units, each with an adder (FADD) and a multiplier (FMUL). Additionally, one of the functional units contains a graphics unit (VIS). Two floating-point instructions can be scheduled out of order each cycle, one to each functional unit. A peak performance of 4 GFLOP is achieved by scheduling two floating-point multiply add (FMA) instructions each cycle. The FADD unit is fully pipelined and can execute an addition, subtraction, conversion, or compare instruction every cycle. The FMUL unit executes pipelined multiply instructions. Divide and square-root instructions are executed with multiple iterations through the multiplier pipeline. The VIS unit is also pipelined and executes SIMD fixed-point graphics instructions. The adder and multiplier have latencies of 3 and 4 cycles respectively. Novel techniques are presented in the adder and multiplier implementations to reduce area and cycle time. The FPU provides RAS support for enhanced server reliability by using selective parity error detection. The FPU has been implemented in 0.15 u, 6-layer metal CMOS technology.","PeriodicalId":356830,"journal":{"name":"Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121321675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 35

Bit-parallel systolic modular multipliers for a class of GF(2/sup m/) 一类GF(2/sup m/)的位并行收缩模乘法器

Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001 Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.930103

Chiou-Yng Lee, E. Lu, Jau-Yien Lee

{"title":"Bit-parallel systolic modular multipliers for a class of GF(2/sup m/)","authors":"Chiou-Yng Lee, E. Lu, Jau-Yien Lee","doi":"10.1109/ARITH.2001.930103","DOIUrl":"https://doi.org/10.1109/ARITH.2001.930103","url":null,"abstract":"In this paper, an effective algorithm for computing multiplication over a class of GF(2/sup m/) based on irreducible all one polynomials (AOP) and equally spaced polynomials (ESP) is presented. The structures are the use of two special operations, called the cyclic shifting and the inner product, to construct the low-latency bit-parallel systolic multipliers. The circuits are simple and modular which is important for hardware implementation. The AOP-based multiplier is composed of (m+1)/sup 2/ identical cells, each of which consisting of one 2-bit AND gate, one 2-bit XOR gate and three 1-bit latches. This multiplier has very low latency and propagation delay, which makes them very fast. Moreover, the AOP-based multiplier of small size can also be applied to construct ESP-based multiplier of large size, in which the elements are represented with the root of an irreducible equally spaced polynomial of degree nr. It is shown that if, for a certain degree, an irreducible ESP of a large degree can be obtained from a corresponding irreducible AOP of a very small degree, then from the complexity point view, the structure of the ESP-based multiplier is beneficial to construct a modular architecture.","PeriodicalId":356830,"journal":{"name":"Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121789969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4