2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.最新文献_第8页

Performing speech recognition on multiple parallel files using continuous hidden Markov models on an FPGA 在FPGA上使用连续隐马尔可夫模型对多个并行文件进行语音识别

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings. Pub Date : 2002-12-16 DOI: 10.1109/FPT.2002.1188720

S. Melnikoff, S. Quigley, M. Russell

引用次数: 12

FPGA based real-time adaptive filtering for space applications 基于FPGA的空间应用实时自适应滤波

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings. Pub Date : 1900-01-01 DOI: 10.1109/FPT.2002.1188702

S. J. Visser, Anwar S. Dawood, John A. Williams

{"title":"FPGA based real-time adaptive filtering for space applications","authors":"S. J. Visser, Anwar S. Dawood, John A. Williams","doi":"10.1109/FPT.2002.1188702","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188702","url":null,"abstract":"Satellites and other space-based signal processing systems face a challenging operating environment. In addition to radiation related effects, the satellites themselves are often electrically noisy, resulting in high levels of noise and interference in data signals. Digital signal processing systems such as adaptive filters are vital components for the next generation of satellites. Most current satellite systems have limited computing resources for on-board digital signal processing and lack flexibility to adapt to changing operation requirements. The deployment of reconfigurable field programmable gate array (FPGA) technology on-board satellites is a very promising solution for digital signal processing in space, as they offer flexibility, scalability and high performance. The high performance computing (HPC-I) payload integrated into the Australian scientific mission satellite FedSat is designed to evaluate the deployment of FPGA technology for a variety of space applications. This paper elaborates on implementing rule-based adaptive filtering techniques on FPGAs for space applications, presenting the design and implementation of an adaptive finite impulse response (FIR) filter on HPC-I. A fuzzy adaptive image filtering algorithm for remote sensing applications is also considered.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126709773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

On-board satellite image compression using reconfigurable FPGAs 基于可重构fpga的星载卫星图像压缩

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings. Pub Date : 1900-01-01 DOI: 10.1109/FPT.2002.1188698

Anwar S. Dawood, John A. Williams, S. J. Visser

{"title":"On-board satellite image compression using reconfigurable FPGAs","authors":"Anwar S. Dawood, John A. Williams, S. J. Visser","doi":"10.1109/FPT.2002.1188698","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188698","url":null,"abstract":"Remote sensing satellites operate almost exclusively in a store-and-forward mode, with acquired imagery stored on board until being downlinked when ground stations come within view. Space-borne imaging sensors generate tremendous volumes of data at very high rates, however storage capacity and communication bandwidth are expensive satellite resources. By compressing the images as they are acquired, better use is made of available storage and bandwidth capacity. Reconfigurable computing technology, which combines the flexibility of traditional microprocessors with the performance of ASIC devices, is very promising for space applications. The High Performance Computing (HPC-I) payload, based on a radiation hardened reconfigurable FPGA has been developed and integrated into the Australian scientific mission satellite FedSat. HPC-I is a testbed in space to validate reconfigurable logic for a variety of satellite applications. The design and implementation on HPC-I of the On-Board Image Compression System (OBICS) is presented, and its compression performance evaluated using JPEG standard as a benchmark. The results indicate that FPGAs and HPC-I are suitable platforms for such systems, and that satisfactory compression can only be achieved with moderately complex logic designs.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116616818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

Enabling technologies for reconfigurable system-on-chip 可重新配置的片上系统使能技术

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings. Pub Date : 1900-01-01 DOI: 10.1109/FPT.2002.1188711

N. Bergmann

引用次数: 4

DRESC: a retargetable compiler for coarse-grained reconfigurable architectures DRESC:用于粗粒度可重构架构的可重目标编译器

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings. Pub Date : 1900-01-01 DOI: 10.1109/FPT.2002.1188678

B. Mei, S. Vernalde, D. Verkest, H. Man, R. Lauwereins

引用次数: 227

FPGA education and research activities in Taiwan 台湾FPGA教育与研究活动

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings. Pub Date : 1900-01-01 DOI: 10.1109/FPT.2002.1188732

Yu-Tsang Chang, Yu-Te Chou, W. Tsai, J. Wang, Chen-Yi Lee

{"title":"FPGA education and research activities in Taiwan","authors":"Yu-Tsang Chang, Yu-Te Chou, W. Tsai, J. Wang, Chen-Yi Lee","doi":"10.1109/FPT.2002.1188732","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188732","url":null,"abstract":"The role of Chip Implementation Center (CIC), founded in 1992 under the National Science Council (NSC) of Taiwan R.O.C., is to provide the services for the fabrication of multi-project chip (MPC), the procurement/integration of software CAD tools, and the promotion of IC and FPGA design/testing/CAD software technology for academia in Taiwan. To date, CIC assisted 86 universities and polytechnics to install over 6000 academic licenses of FPGA design and verification tools. Moreover, CIC promotes various training courses intensively and periodically for the FPGA design flow. In year 2002, 8 kinds of courses with over 25 classes are provided to meet the demands from academia sites. More than 1000 students are trained in these classes. The FPGA design flow, provided by CIC, is used in many of researches for implementation, verification, and prototypes. Based on the demands of academics, CIC will build a laboratory for rapid prototyping system-level design. In this laboratory, SoC (System on a Chip) and IP (Intellectual Property) designs can be downloaded into FPGA to work with a processor to verification on an SOPC (System on Programmable Chip) environment.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128590058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Strassen's matrix multiplication for customisable processors 可定制处理器的Strassen矩阵乘法

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings. Pub Date : 1900-01-01 DOI: 10.1109/FPT.2002.1188734

H. Ip, James D. Low, P. Cheung, G. Constantinides, W. Luk, S. P. Seng, P. Metzgen

引用次数: 4

FPGA-based cloud detection for real-time onboard remote sensing 基于fpga的实时机载遥感云检测

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings. Pub Date : 1900-01-01 DOI: 10.1109/FPT.2002.1188671

John A. Williams, Anwar S. Dawood, S. J. Visser

引用次数: 45