DRESC:用于粗粒度可重构架构的可重目标编译器

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings. Pub Date : 1900-01-01 DOI:10.1109/FPT.2002.1188678

B. Mei, S. Vernalde, D. Verkest, H. Man, R. Lauwereins

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引用次数: 227

摘要

近年来，粗粒度的可重构体系结构变得越来越重要。自动设计或编译工具对它们的成功至关重要。在本文中，我们提出了一种针对一类粗粒度可重构架构的可重目标编译器。讨论了几个关键问题。程序分析和转换为调度准备数据流。体系结构抽象从具体的体系结构描述生成内部图形表示。模调度算法是开发并行性和实现高性能的关键。实验结果表明，在测试的内核上，每周期指令(IPC)高达28.7条。

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DRESC: a retargetable compiler for coarse-grained reconfigurable architectures

Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compiling tools are essential to their success. In this paper, we present a retargetable compiler for a family of coarse-grained reconfigurable architectures. Several key issues are addressed. Program analysis and transformation prepare dataflow for scheduling. Architecture abstraction generates an internal graph representation from a concrete architecture description. A modulo scheduling algorithm is key to exploit parallelism and achieve high performance. The experimental results show up to 28.7 instructions per cycle (IPC) over tested kernels.

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来源期刊

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.

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