On-board satellite image compression using reconfigurable FPGAs

Abstract

Remote sensing satellites operate almost exclusively in a store-and-forward mode, with acquired imagery stored on board until being downlinked when ground stations come within view. Space-borne imaging sensors generate tremendous volumes of data at very high rates, however storage capacity and communication bandwidth are expensive satellite resources. By compressing the images as they are acquired, better use is made of available storage and bandwidth capacity. Reconfigurable computing technology, which combines the flexibility of traditional microprocessors with the performance of ASIC devices, is very promising for space applications. The High Performance Computing (HPC-I) payload, based on a radiation hardened reconfigurable FPGA has been developed and integrated into the Australian scientific mission satellite FedSat. HPC-I is a testbed in space to validate reconfigurable logic for a variety of satellite applications. The design and implementation on HPC-I of the On-Board Image Compression System (OBICS) is presented, and its compression performance evaluated using JPEG standard as a benchmark. The results indicate that FPGAs and HPC-I are suitable platforms for such systems, and that satisfactory compression can only be achieved with moderately complex logic designs.