2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)最新文献_第5页

Interfacing of Digital and Resolver Type Systems for Transmission of Heading Angle 数字式和旋转式系统在航向角传输中的接口

2021 8th International Conference on Signal Processing and Integrated Networks (SPIN) Pub Date : 2021-08-26 DOI: 10.1109/SPIN52536.2021.9565978

Vijendra Kumar Singh, Y. Sharma

{"title":"Interfacing of Digital and Resolver Type Systems for Transmission of Heading Angle","authors":"Vijendra Kumar Singh, Y. Sharma","doi":"10.1109/SPIN52536.2021.9565978","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9565978","url":null,"abstract":"A marine vessel platform is fitted with sensors and equipments of diverse origin which are required to work in tandem in order to enhance its operation capability. However, due to incompatibilities in the data formats and protocols that are used, these equipments/ sensors cannot be integrated directly. As the systems available are a mixture of digital and analog types, this paper details the design and development of Embedded Interfacing Solution for interfacing of Digital and Resolver type systems for transmission of An embedded interfacing board was using Cadence OrCAD proprietary subsequently implemented using 8051, Digital to Resolver converter modules, low power operational amplifiers and other required components. This electronic embedded interfacing board converts the digital input containing heading angle into Analog Resolver type of output. This was tested using simulated heading angle created with the help of COM Port Toolkit software application and the output of this embedded interfacing solution was measured on Angle Position Indicator (API) and with the help of Oscilloscope.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133246183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Voltage Profile Enhancement of a 33 Bus System Integrated with Renewable Energy Sources and Electric Vehicle 可再生能源和电动汽车集成33总线系统的电压分布增强

2021 8th International Conference on Signal Processing and Integrated Networks (SPIN) Pub Date : 2021-08-26 DOI: 10.1109/SPIN52536.2021.9566111

Aishwarya Tripathy, M. M. Kar

引用次数: 1

Pulse Width Modulation controller based Thermal Stabilization for Iodine evaporation inflowing chemical laser 基于脉宽调制控制器的碘蒸发流入化学激光器热稳定

2021 8th International Conference on Signal Processing and Integrated Networks (SPIN) Pub Date : 2021-08-26 DOI: 10.1109/SPIN52536.2021.9565952

R. Dohare, Mainuddin, G. Singhal

{"title":"Pulse Width Modulation controller based Thermal Stabilization for Iodine evaporation inflowing chemical laser","authors":"R. Dohare, Mainuddin, G. Singhal","doi":"10.1109/SPIN52536.2021.9565952","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9565952","url":null,"abstract":"Present paper focuses upon development of thermal stabilization scheme based on pulse width modulation (PWM) controller used for iodine evaporation in flowing chemical laser. Iodine acts a lasing medium in chemical oxygen iodine laser (COIL). In COIL, iodine crystals are put in iodine chambers and needs to be continuously evaporated in order to get vapor iodine. For efficient COIL operation, stabilized iodine evaporation is one of the prime needs. In addition, iodine transportation lines are also required to be heated to ~ 75°C-85°C in order to restrict the iodine deposition during transport. Iodine being hazardous to human beings, the said thermal operation has to be continuously monitored and controlled to provide uniform flow of iodine during safe laser operation. Thermal actions are performed by using several rod heaters and belt heaters. A PWM controller based in house thermal stabilization scheme has been developed using feedback mechanism for iodine evaporation with an accuracy of ±0.5°C instead of using commercially available controllers. It comprises of Operational Amplifier LF 356, Instrumentation Amplifier (IA) AD 620, LM 339 Comparator ICs, K type thermocouple and solid state relay (SSR).The developed hardware has been interfaced with data acquisition system (DAS) and all the temperatures were monitored and recorded online.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"33 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116391613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Detection and Localization of Tampered Image using Hash Functions* 基于哈希函数的篡改图像检测与定位*

2021 8th International Conference on Signal Processing and Integrated Networks (SPIN) Pub Date : 2021-08-26 DOI: 10.1109/SPIN52536.2021.9566130

Arpan Gupta, Amit Kumar, Tarun Chaudhary, Alka Leekha

引用次数: 1

A Novel Low Power Design of Brent Kung Adder Having Fault Tolerant Capability 一种具有容错能力的新型低功耗Brent Kung加法器设计

2021 8th International Conference on Signal Processing and Integrated Networks (SPIN) Pub Date : 2021-08-26 DOI: 10.1109/SPIN52536.2021.9566135

Sumit Pahuja, Gurjit Kaur

{"title":"A Novel Low Power Design of Brent Kung Adder Having Fault Tolerant Capability","authors":"Sumit Pahuja, Gurjit Kaur","doi":"10.1109/SPIN52536.2021.9566135","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566135","url":null,"abstract":"In today’s technology, Parallel Prefix Adders is widely used in VLSI to get higher delay performance. The demand for adders that use reversible logic gates is growing every day as technology advances. However, since reversible logic gates have no information loss, reversible circuits consume less heat than conventional circuits. Reversible logic gates along with extra characteristics that input parity and output parity are equal is termed as PPRLG (parity preserving reversible logic gates). This characteristic allows any device to function normally even if any intermediary nodes fail. The Brent-Kung adder offers a faster response time as compared to many adders. As a consequence, designing an extremely fast, fault-tolerable, and low-power adder immediately results in increased device speed for quicker computing purposes, so Brent Kung adder with the help of PPRLG is presented in our work. The suggested Adder implementation is done using Verilog programming language in the Xilinx software with version 14.7. For the purpose of demonstration of its quality, presented Parity Preserving Reversible Adder, including many sub-parts, we used a number of parameters like Quantum-Cost, CI, GC, and Unused Output, including the schematic (Register Transfer Level) of the Brent-Kung Adder and its sub-parts. So yet, no Brent-Kung adder circuit employing Reversible Logic Gates with Fault-Tolerant capabilities has been suggested, to the best of our knowledge.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115555233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Diabetes Type2 Patient Detection Using LASSO Based CFFNN Machine Learning Approach 基于LASSO的CFFNN机器学习方法检测2型糖尿病患者

2021 8th International Conference on Signal Processing and Integrated Networks (SPIN) Pub Date : 2021-08-26 DOI: 10.1109/SPIN52536.2021.9565965

Sandeep Tiwari, Nitesh Gupta, Pranay Yadav

引用次数: 11

Miller Compensated Op-Amp Design for High PSRR & High Gain of 72dB in 180-nm CMOS Process 180nm CMOS工艺中72dB高PSRR高增益的Miller补偿运算放大器设计

2021 8th International Conference on Signal Processing and Integrated Networks (SPIN) Pub Date : 2021-08-26 DOI: 10.1109/SPIN52536.2021.9565966

Abdul Qadir Khan, Harshit Yadav, Paurush Bhulania

{"title":"Miller Compensated Op-Amp Design for High PSRR & High Gain of 72dB in 180-nm CMOS Process","authors":"Abdul Qadir Khan, Harshit Yadav, Paurush Bhulania","doi":"10.1109/SPIN52536.2021.9565966","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9565966","url":null,"abstract":"Design of two stage Complementry Metal Oxide Semiconductor Operational amplifier has presented in this work, where the OpAmp is designed on T-SPICE with the help of 180 nm technology, also with miller compensation technique for large gain and PSRR. On incorporating the components of external feedback deployment, the op-amp can be utilized for a many applications e.g. in amplifications in ac & dc signals, oscillators, filters, regulators, comparators & other circuits. In this work, emphasis is given for achieving product of a large gain & also higher gain bandwidth. Work has been for obtaining a higher stability value in terms of Phase Margin & less dissipating power. Number of simulations had been presented for testing the targeted parameters, confirming a 72 dB gain with 51 MHz GBW. The phase margin of 57° have attained along with a slew rate value of 24 V/μs. The design & various simulations had carried out for validating the performance of power dissipation having value 290 μW & value of PSRR as 94.66 dB. With all results, the proposed Op-Amp provides a good use in comparator & other data converting services.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121988318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Figure of Merit Analysis of LRSPR Sensor using Graphene in NIR Regime 在近红外波段使用石墨烯的LRSPR传感器的优点分析图

2021 8th International Conference on Signal Processing and Integrated Networks (SPIN) Pub Date : 2021-08-26 DOI: 10.1109/SPIN52536.2021.9566024

Narendra Pal, J. Maurya, Y. Prajapati

引用次数: 0

Parasitic Extraction and Performance Assessment using Experimental Analysis of rGO Interconnects for PCB Designs 基于实验分析的PCB设计中rGO互连的寄生提取和性能评估

2021 8th International Conference on Signal Processing and Integrated Networks (SPIN) Pub Date : 2021-08-26 DOI: 10.1109/SPIN52536.2021.9566006

Vishank Makhe, Vinay S. Palaparthy, Yash Agrawal

引用次数: 0

A Comparative Analysis of DC - DC Boost Converter Voltages for Renewable Electrolysis 可再生电解用DC - DC升压变换器电压的比较分析

2021 8th International Conference on Signal Processing and Integrated Networks (SPIN) Pub Date : 2021-08-26 DOI: 10.1109/SPIN52536.2021.9566103

Sheetal Chauhan, M. A. Ansari, O. Singh

{"title":"A Comparative Analysis of DC - DC Boost Converter Voltages for Renewable Electrolysis","authors":"Sheetal Chauhan, M. A. Ansari, O. Singh","doi":"10.1109/SPIN52536.2021.9566103","DOIUrl":"https://doi.org/10.1109/SPIN52536.2021.9566103","url":null,"abstract":"The process that is responsible for changing a particular DC voltage to another DC voltage is termed as DC- to-DC voltage conversion. There are three types of DC-to-DC power converters. They are Buck Converter, Boost Converter and Buck-Boost Converter. Buck converter steps down voltage from its input to its output while a buck-boost converter maintains higher or lower output, which depends on the source voltage. A boost converter is a system where voltage at the output terminal is higher than the source voltage. It is generally referred by the name \"step-up\" converter because of its source voltage stepping up capability. Since, power must always be conserved; current at the output terminal is lower than the current at the input terminal. Power requirement for the boost converter can be fulfilled using some efficient DC source, such as batteries, PV panels and DC generators. Boost converter finds application in consumer electronics, DC motor drives, photovoltaic systems and so on. This paper presents a detailed analysis of DC-to-DC boost converter voltages for renewable electrolysis. The paper presents two circuit topologies of the boost converter viz. one with transformer and the other without transformer. A comparative analysis of these circuit topologies is done and MATLAB simulation results are obtained. It has been proved that the topology using a voltage-matching transformer of high frequency is better. In the analysis, the topology with transformer is proved better for renewable electrolysis due to its regulated output voltage and ripple-free characteristic.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123505294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1