A Novel Low Power Design of Brent Kung Adder Having Fault Tolerant Capability

Abstract

In today’s technology, Parallel Prefix Adders is widely used in VLSI to get higher delay performance. The demand for adders that use reversible logic gates is growing every day as technology advances. However, since reversible logic gates have no information loss, reversible circuits consume less heat than conventional circuits. Reversible logic gates along with extra characteristics that input parity and output parity are equal is termed as PPRLG (parity preserving reversible logic gates). This characteristic allows any device to function normally even if any intermediary nodes fail. The Brent-Kung adder offers a faster response time as compared to many adders. As a consequence, designing an extremely fast, fault-tolerable, and low-power adder immediately results in increased device speed for quicker computing purposes, so Brent Kung adder with the help of PPRLG is presented in our work. The suggested Adder implementation is done using Verilog programming language in the Xilinx software with version 14.7. For the purpose of demonstration of its quality, presented Parity Preserving Reversible Adder, including many sub-parts, we used a number of parameters like Quantum-Cost, CI, GC, and Unused Output, including the schematic (Register Transfer Level) of the Brent-Kung Adder and its sub-parts. So yet, no Brent-Kung adder circuit employing Reversible Logic Gates with Fault-Tolerant capabilities has been suggested, to the best of our knowledge.