2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)最新文献_第2页

Mobile solar aerator 移动式太阳能曝气机

2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-19 DOI: 10.1109/RTEICT.2017.8256547

K. Muralidhar, Amal Nair, G. Poornima, N. Akshay, K. G. Anjan, Gangatkar R R Arun

{"title":"Mobile solar aerator","authors":"K. Muralidhar, Amal Nair, G. Poornima, N. Akshay, K. G. Anjan, Gangatkar R R Arun","doi":"10.1109/RTEICT.2017.8256547","DOIUrl":"https://doi.org/10.1109/RTEICT.2017.8256547","url":null,"abstract":"Oxygen is main essential need of survival not only on land but also in water body. Life of aquatic organisms depends on it. Due to increase in human population and industrial waste, the indulgence of waste materials into the water body leads adverse effect on percentage of dissolved oxygen. With this the scarcity of life also increases. There are many methods introduced to increase the dissolved oxygen level in water. The implementations are difficult and highly expensive. Also, the implementations are fixed for certain boundary. Aeration is one of the processes that increases the dissolved oxygen level and helps in circulation of water. The aerators invented till now are stationary. They are powered by external supply which makes it a main constraint to be fixed for a boundary. This paper proposes an innovative idea of aeration using renewable energy for the process and making it mobile would make it more efficient and economical. Using solar panels to power the aerator and robotics technology for movement of aerator makes it more reliable and efficient. This kind of implementation gives control over the movement of aerator. The whole process was analyzed, experimentally tested and modeled from view point of informatics, simulations and flowcharts for optimization before the final implementation.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125631060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and performance analysis of 2:1 multiplexer using multiple logic families at 180 nm technology 采用多个逻辑系列的180nm工艺的2:1多路复用器的设计与性能分析

2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-19 DOI: 10.1109/RTEICT.2017.8256918

Rose V Anugraha, Devi S Durga, R. Avudaiammam

{"title":"Design and performance analysis of 2:1 multiplexer using multiple logic families at 180 nm technology","authors":"Rose V Anugraha, Devi S Durga, R. Avudaiammam","doi":"10.1109/RTEICT.2017.8256918","DOIUrl":"https://doi.org/10.1109/RTEICT.2017.8256918","url":null,"abstract":"Since multiplexer (MUX) is one of the important components of communication system, to increase the efficiency of data transmission, to utilize the vast memory space of a computer in an effective way and to convert parallel form of data into serial form in telecommunication networks an efficient design of low power-delay MUX is required. Hence in this work, a basic 2:1 MUX is designed using various CMOS logic families such as Static CMOS logic, Pseudo NMOS logic, Domino logic and Dual-Rail Domino logic to identify the best logic family suitable for the design of higher levels of MUX. The implementation is done in VLSI technology as it has features like small size, low cost, high operating speed and low power. The performance analysis of the MUX using various CMOS logic families are conducted using VLSI back-hand tool: CADENCE VIRTUOSO SCHEMATIC EDITOR 6.1 at 180nm. The results obtained show that, the Domino logic based 2:1 MUX is the most efficient design because the average power consumption is 20.06% and PDP(Power Delay Product) is 20.1% lesser than that of other logic familes. But trade-offs are inferred between Domino logic and Static CMOS logic which can be neglected on considering the overall performance. Since the Domino logic outperforms the other logic families, this work suggests that any higher level MUX with low power-delay and PDP can be achieved using Domino logic.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133608742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Factors inhibiting the adoption of DevOps in large organisations: South African context 阻碍大型组织采用DevOps的因素:南非背景

2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-19 DOI: 10.1109/RTEICT.2017.8256556

Morgan B. Kamuto, J. Langerman

{"title":"Factors inhibiting the adoption of DevOps in large organisations: South African context","authors":"Morgan B. Kamuto, J. Langerman","doi":"10.1109/RTEICT.2017.8256556","DOIUrl":"https://doi.org/10.1109/RTEICT.2017.8256556","url":null,"abstract":"DevOps has been identified as a phenomenon whereby stakeholders of a software development team work together to deliver software continuously, allowing the business to seize emerging and existing market opportunities while reducing the time required for inclusion of client feedback. However, little has been done to develop adoption strategies/frameworks for this phenomenon. The absence of such strategies may result in DevOps not being adequately communicated and its impact not fully comprehended in both the practitioner and academic research communities. This study investigates the factors that are hindering the adoption of DevOps and proposes strategies to address them using both literature study and interviews with practitioners actively involved in the DevOps movement. Five main factors hindering the adoption of DevOps are identified: lack of strategic direction from senior management; lack of education around DevOps; risk of disintermediation of roles; resistance to change and silo mentality. A proposed conceptual framework has been developed both to strategize the adoption of DevOps, and to contribute input for future research.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122758345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31

Small signal stability assessment of a DFIG based wind power systems 基于DFIG的风电系统小信号稳定性评估

2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-19 DOI: 10.1109/RTEICT.2017.8256553

Jawaharlal Bhukya, V. Mahajan

引用次数: 1

Design and development of maximum power point tracking algorithm using field programmable gate array 基于现场可编程门阵列的最大功率点跟踪算法的设计与开发

2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-19 DOI: 10.1109/RTEICT.2017.8256860

Suman Sharma, A. Deshpande

引用次数: 1

Kappa and accuracy evaluations of machine learning classifiers 机器学习分类器的Kappa和准确性评估

2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-19 DOI: 10.1109/RTEICT.2017.8256551

B. Sasikala, V. Biju, C. Prashanth

引用次数: 18

Short term stock price prediction using deep learning 利用深度学习进行短期股价预测

2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-19 DOI: 10.1109/RTEICT.2017.8256643

K. Khare, Omkar Darekar, Prafulla Gupta, V. Attar

{"title":"Short term stock price prediction using deep learning","authors":"K. Khare, Omkar Darekar, Prafulla Gupta, V. Attar","doi":"10.1109/RTEICT.2017.8256643","DOIUrl":"https://doi.org/10.1109/RTEICT.2017.8256643","url":null,"abstract":"Short — term price movements, contribute a considerable measure to the unpredictability of the securities exchanges. Accurately predicting the price fluctuations in stock market is a huge economical advantage. The aforementioned task is generally achieved by analyzing the company, this is called as fundamental analysis. Another method, which is undergoing a lot of research work recently, is to create a predictive algorithmic model using machine learning. To train machines to take trading decisions in such short — period of time, the latter method needs to be adopted. Deep Neural Networks, being the most exceptional innovation in Machine Learning, have been utilized to develop a short-term prediction model. This paper plans to forecast these short — term prices of stocks. 10 unique stocks recorded on New York Stock Exchange are considered for this review. The review essentially focuses on the prediction of these short — term prices leveraging the power of technical analysis. Technical Analysis guides the framework to understand the patterns from the historical prices fed into it, and attempts to probabilistically forecast the fleeting future prices of the stock under review. The paper discusses about two distinct sorts of Artificial Neural Networks, Feed Forward Neural Networks and Recurrent Neural Networks. The review uncovers that Feed Forwards Multilayer Perceptron perform superior to Long Short-Term Memory, at predicting the short — term prices of a stock.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132524502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 58

Obstacle aware delay optimized rectilinear steiner minimum tree routing 障碍感知延迟优化的线性斯坦纳最小树路由

2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-19 DOI: 10.1109/RTEICT.2017.8256989

G. Shyamala, G. R. Prasad

{"title":"Obstacle aware delay optimized rectilinear steiner minimum tree routing","authors":"G. Shyamala, G. R. Prasad","doi":"10.1109/RTEICT.2017.8256989","DOIUrl":"https://doi.org/10.1109/RTEICT.2017.8256989","url":null,"abstract":"This research work present a method to solve the problem of constructing Rectilinear Steiner Minimum Tree (RSMT) for a group of pins in the presence of obstacles. In modern very large-scale integrated circuit (VLSI) designs, the obstacles, generally blocks the metal and the device layer. Therefore routing on top of blockage is a possible solution but buffers cannot be placed over the obstacle. Modern VLSI design OARSMT construction has long wire length, which results in signal violation. To address this issue, a slew constraint interconnect need to be considered in routing over obstacle. This is called the Obstacle-Avoiding Rectilinear Steiner minimum tree (OARSMT) problem with slew constraints over obstacles. The drawback of traditional OARSMT is that they only consider slew constraint, and delay constraint is neglected. It induces high routing resources overhead due to buffer insertion and does not solve global routing solution. This work presents an Obstacle Aware Delay Optimized Rectilinear Steiner Minimum Tree (OADORSMT) Routing to address the delay, slew constraint and reduce the routing resources. Experiments are conduced to evaluate the performance of proposed approach over existing approach in term of wire length and worst negative slack. The experiments are conducted for small and large nets considering obstacles and outcome shows the proposed efficiency over existing approaches.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129429886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Modeling, simulation and analysis of common mode voltage, bearing voltage and bearing current in PWM multilevel inverter fed induction motor with long cable 长电缆PWM多电平逆变馈电动机共模电压、轴承电压和轴承电流的建模、仿真与分析

2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-19 DOI: 10.1109/RTEICT.2017.8256781

P. Sunitha, B. Banakara, Sharana Reddy

引用次数: 5

Design and simulation of synchronous buck converter for LED application LED同步降压变换器的设计与仿真

2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Pub Date : 2017-05-19 DOI: 10.1109/RTEICT.2017.8256574

C. Deekshitha, K. L. Shenoy

引用次数: 8