Design and performance analysis of 2:1 multiplexer using multiple logic families at 180 nm technology

Abstract

Since multiplexer (MUX) is one of the important components of communication system, to increase the efficiency of data transmission, to utilize the vast memory space of a computer in an effective way and to convert parallel form of data into serial form in telecommunication networks an efficient design of low power-delay MUX is required. Hence in this work, a basic 2:1 MUX is designed using various CMOS logic families such as Static CMOS logic, Pseudo NMOS logic, Domino logic and Dual-Rail Domino logic to identify the best logic family suitable for the design of higher levels of MUX. The implementation is done in VLSI technology as it has features like small size, low cost, high operating speed and low power. The performance analysis of the MUX using various CMOS logic families are conducted using VLSI back-hand tool: CADENCE VIRTUOSO SCHEMATIC EDITOR 6.1 at 180nm. The results obtained show that, the Domino logic based 2:1 MUX is the most efficient design because the average power consumption is 20.06% and PDP(Power Delay Product) is 20.1% lesser than that of other logic familes. But trade-offs are inferred between Domino logic and Static CMOS logic which can be neglected on considering the overall performance. Since the Domino logic outperforms the other logic families, this work suggests that any higher level MUX with low power-delay and PDP can be achieved using Domino logic.