2010 International Workshop on Innovative Architecture for Future Generation High Performance最新文献

[2010] VIX: A Router Architecture for Priority-Aware Networks-on-Chip [2010]一种基于优先级感知的片上网络结构

2010 International Workshop on Innovative Architecture for Future Generation High Performance Pub Date : 2010-01-17 DOI: 10.1109/IWIA.2010.15

Takuma Kogo, N. Yamasaki

引用次数: 1

[2010] OREX - An Optical Ring with Electrical Crossbar Hybrid Photonic Network-on-Chip [2010]光环与电交叉棒混合光子片上网络

2010 International Workshop on Innovative Architecture for Future Generation High Performance Pub Date : 2010-01-17 DOI: 10.1109/IWIA.2010.13

Cisse Ahmadou Dit Adi, Ping Qiu, H. Irie, T. Miyoshi, T. Yoshinaga

引用次数: 1

[2009] A Stage-Level Recovery Scheme in Scalable Pipeline Modules for High Dependability [2009]高可靠性可扩展管道模块的阶段级恢复方案

2010 International Workshop on Innovative Architecture for Future Generation High Performance Pub Date : 2010-01-17 DOI: 10.1109/IWIA.2010.11

Jun Yao, Hajime Shimada, Kazutoshi Kobayashi

{"title":"[2009] A Stage-Level Recovery Scheme in Scalable Pipeline Modules for High Dependability","authors":"Jun Yao, Hajime Shimada, Kazutoshi Kobayashi","doi":"10.1109/IWIA.2010.11","DOIUrl":"https://doi.org/10.1109/IWIA.2010.11","url":null,"abstract":"In the recent years, the increasing error rate has become one of the major impediments for the application of new process technologies in electronic devices like microprocessors. This thereby necessitates the research of fault toleration mechanisms from all device, micro-architecture and system levels to keep correct computation in future microprocessors, along the advances of process technologies.Space redundancy, as dual or triple modular redundancy (DMR or TMR), is widely used to tolerate errors with a negligible performance loss. In this paper, at the micro-architecture level, we propose a very fine-grained recovery scheme based on a DMR processor architecture to cover every transient error inside of the memory interface boundary. Our recovery method makes full use of the existing duplicated hardware in the DMR processor, which can avoid large hardware extension by not using checkpoint buffers in many fault-tolerable processors. The hardware-based recovery is achieved by dynamically triggering an instruction re-execution procedure in the next cycle after error detection, which indicates a near-zero performance impact to achieve an error-free execution.A TMR architecture is usually preferred as it provides a seamless error correction by a majority voting logic and therefore generates no recovery delay. With our fast recovery scheme at a low hardware cost, our result shows that even under a relatively high transient error rate, it is possible to only use a DMR architecture to detect/recover errors at a negligible performance cost. Our reliable processor is thus constructed to use a DMR execution with the fast recovery as its major working mode. It saves around 1/3 energy consumption from a traditional TMR architecture, while the transient error coverage is still maintained.","PeriodicalId":339844,"journal":{"name":"2010 International Workshop on Innovative Architecture for Future Generation High Performance","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126490912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

[2010] Facing the Exascale Energy Wall [2010]“百亿亿次能源墙”

2010 International Workshop on Innovative Architecture for Future Generation High Performance Pub Date : 2010-01-17 DOI: 10.1109/IWIA.2010.9

P. Kogge, P. Fratta, Megan Vance

引用次数: 10

[2009] Exploring the Possible Past Futures of a Single Part Type Multi-core PIM Chip [2009]单零件型多核PIM芯片的未来发展

2010 International Workshop on Innovative Architecture for Future Generation High Performance Pub Date : 2010-01-17 DOI: 10.1109/IWIA.2010.8

P. Kogge

引用次数: 2

[2009] An Instruction Decomposition Method for Reconfigurable Decoders [2009]一种可重构解码器的指令分解方法

2010 International Workshop on Innovative Architecture for Future Generation High Performance Pub Date : 2010-01-17 DOI: 10.1109/IWIA.2010.12

Kazuhiro Yoshimura, Takashi Nakada, Y. Nakashima

引用次数: 0

[2010] Energy Efficiency Using Loop Buffer based Instruction Memory Organizations [2010]基于循环缓冲的指令存储器组织的能源效率研究

2010 International Workshop on Innovative Architecture for Future Generation High Performance Pub Date : 2010-01-17 DOI: 10.1109/IWIA.2010.10

Antonio Artés, F. Duarte, M. Ashouei, J. Huisken, J. Ayala, David Atienza Alonso, F. Catthoor

{"title":"[2010] Energy Efficiency Using Loop Buffer based Instruction Memory Organizations","authors":"Antonio Artés, F. Duarte, M. Ashouei, J. Huisken, J. Ayala, David Atienza Alonso, F. Catthoor","doi":"10.1109/IWIA.2010.10","DOIUrl":"https://doi.org/10.1109/IWIA.2010.10","url":null,"abstract":"Energy consumption in embedded systems is strongly dominated by instruction memory organizations. Based on this, any architectural enhancement introduced in this component will produce a significant reduction of the total energy bud-get of the system. Loop buffering is an effective scheme to reduce the energy consumption of the instruction memory organization.In this paper, a novel classification of architectural enhancements based on the use of loop buffer concept is presented. Using this classification, an energy design space exploration is performed to show the impact in the energy consumption on different application scenarios. From gate-level simulations, the energy analysis demonstrates that the instruction level parallelism of the system brings not only improvements in performance, but also improvements in the energy consumption of the system.The increase in instruction level parallelism makes easy the adaptation of the sizes of the loop buffers to the sizes of the loops that form the application, because gives more freedom to combine the execution of the loops that form the application.","PeriodicalId":339844,"journal":{"name":"2010 International Workshop on Innovative Architecture for Future Generation High Performance","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128132069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

[2010] Avoiding Side-Channel Attacks in Embedded Systems with Non-deterministic Branches [2010]基于非确定性分支的嵌入式系统侧信道攻击

2010 International Workshop on Innovative Architecture for Future Generation High Performance Pub Date : 2010-01-17 DOI: 10.1109/IWIA.2010.14

P. Malagón, Juan-Mariano de Goyeneche, Marina Zapater, Jose M. Moya

引用次数: 0

[2010] Combined Dynamic-Static Approach for Thermal-Awareness in Heterogeneous Data Centers [2010]基于动态-静态的异构数据中心热感知方法

2010 International Workshop on Innovative Architecture for Future Generation High Performance Pub Date : 2010-01-17 DOI: 10.1109/IWIA.2010.7

Marina Zapater, J. L. Risco-Martín, Z. Bankovic, J. Ayala, Jose M. Moya

引用次数: 0