发布求助
文献互助 智能选刊 最新文献

IEEE European Test Workshop, 2001.最新文献

筛选
英文 中文
Internal feedback bridging faults in combinational CMOS circuits: analysis and testing 组合CMOS电路中的内部反馈桥接故障:分析与测试
IEEE European Test Workshop, 2001. Pub Date : 2001-05-29 DOI: 10.1109/ETW.2001.946655
Y. Miura, S. Seno
{"title":"Internal feedback bridging faults in combinational CMOS circuits: analysis and testing","authors":"Y. Miura, S. Seno","doi":"10.1109/ETW.2001.946655","DOIUrl":"https://doi.org/10.1109/ETW.2001.946655","url":null,"abstract":"We analyze fault behaviors of intemal feedback bridging faults by using a simple circuit model consisting of 2-input NAND gate and NOT gate. From analysis results we find that they are more complex than those associated with extemal feedback bridging faults. We expose that they cause intemal oscillation and IDDQ-only failure as well as latch and oscillation behavior. We also discuss methods for detecting this kind of fault.","PeriodicalId":339694,"journal":{"name":"IEEE European Test Workshop, 2001.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129386821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A packet switching communication-based test access mechanism for system chips 基于分组交换通信的系统芯片测试访问机制
IEEE European Test Workshop, 2001. Pub Date : 2001-05-29 DOI: 10.1109/ETW.2001.946668
M. Nahvi, A. Ivanov
{"title":"A packet switching communication-based test access mechanism for system chips","authors":"M. Nahvi, A. Ivanov","doi":"10.1109/ETW.2001.946668","DOIUrl":"https://doi.org/10.1109/ETW.2001.946668","url":null,"abstract":"In this paper, a Test Access Mechanism (TAM) architecture based on a packet switching communication network is presented. The basic goal is to develop a modular, generic, and configurable TAM.The proposed architecture provides a modular TAM that provides two levels of scalability, i.e., design-version scalability and multi-level scalability. Core access time and interconnect length models and simulation results for the proposed architecture are presented and compared to that of a bus- based TAM.","PeriodicalId":339694,"journal":{"name":"IEEE European Test Workshop, 2001.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125120517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
Automated regression testing of CTI-systems cti系统的自动回归测试
IEEE European Test Workshop, 2001. Pub Date : 2001-05-29 DOI: 10.1109/ETW.2001.946662
Oliver Niese, T. Margaria, A. Hagerer, B. Steffen, Georg Brune, Werner Goerigk, H. Ide
{"title":"Automated regression testing of CTI-systems","authors":"Oliver Niese, T. Margaria, A. Hagerer, B. Steffen, Georg Brune, Werner Goerigk, H. Ide","doi":"10.1109/ETW.2001.946662","DOIUrl":"https://doi.org/10.1109/ETW.2001.946662","url":null,"abstract":"In this paper we present an integrated testing environment for the automated regression test of Computer Telephony Integrated applications.Its novelty consists of a coordinative test management layer that instantiates a general-purpose environment for the specification and verification of workflows in the testing domain.This results in a test environment that controls not only the individual test tools,but also the whole life-cycle of functional system- level tests, comprising test design, test generation, test execution, test evaluation and test reporting.Special attention is devoted to the simplification of the test case design and the checking f admissibility criteria, of interdependencies between the actions of test cases, and of assumptions about the state of the system's resources.We discuss the key features of our testing environment along a concrete industrial application, which illustrates in particular the coarse grain, workflow-like test case representation and the validation and formal verification capabilities. Field results document an efficiency improvement of factors during the test execution phase.","PeriodicalId":339694,"journal":{"name":"IEEE European Test Workshop, 2001.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126060173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Analyzing bridging faults impact on EEPROM cell array 桥接故障对EEPROM单元阵列的影响分析
IEEE European Test Workshop, 2001. Pub Date : 2001-05-29 DOI: 10.1109/ETW.2001.946653
J. Portal, A. Pérez
{"title":"Analyzing bridging faults impact on EEPROM cell array","authors":"J. Portal, A. Pérez","doi":"10.1109/ETW.2001.946653","DOIUrl":"https://doi.org/10.1109/ETW.2001.946653","url":null,"abstract":"The objective of this paper is to present a specific EEPROM functional fault model related to the impact of bridging faults in the array of cells. Moreover, the evolution of these functional faults throughout the useful life of the memory is established. In this aim, a hierarchical overview from the array structure down to the floating gate transistor simulation model is given. A set of bridging faults is defined with their corresponding stimuli. Finally, a representative simulation example is detailed.","PeriodicalId":339694,"journal":{"name":"IEEE European Test Workshop, 2001.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115236174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
System-level DFT for consumer products 消费类产品的系统级DFT
IEEE European Test Workshop, 2001. Pub Date : 1900-01-01 DOI: 10.1109/ETW.2001.946656
D.C.L. van Geest, Febe de Jong
{"title":"System-level DFT for consumer products","authors":"D.C.L. van Geest, Febe de Jong","doi":"10.1109/ETW.2001.946656","DOIUrl":"https://doi.org/10.1109/ETW.2001.946656","url":null,"abstract":"Consumer products like TV, VCR and CD have long been tested with raditional test methods like bed-of-nails and functional testing.The last couple of years this has been extended with JTAG Boundary Scan (IEEE Std 1149.1) because of the growing digital design content. However, Boundary Scan does not cover all pins and therefore will be insufficient in the very near future. An overview will be given of new test solutions that are being developed to deal with this trend.The main strategy is to build test solutions into silicon (DfT). This way, costs scale down with every silicon generation, making it cost-effective in the competitive market of consumer products. At the same time, test access can be kept standard and simple. The test solutions that will be discussed are: testing power & ground connections; testing analogue connections; testing connections to complex memories like DDR SDRAM; testing connections to Flash memories. This set of DfT solutions will significantly increase the test coverage of consumer products without relying on (long) functional tests or expensive test equipment.","PeriodicalId":339694,"journal":{"name":"IEEE European Test Workshop, 2001.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127707436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信