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Microprogrammed implementation of a single chip microprocessor 单片机的微程序实现
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804299
S. Stritter, N. Tredennick
{"title":"Microprogrammed implementation of a single chip microprocessor","authors":"S. Stritter, N. Tredennick","doi":"10.1145/1014198.804299","DOIUrl":"https://doi.org/10.1145/1014198.804299","url":null,"abstract":"This paper considers microprogramming as a tool for implementing large scale integration, single-chip microprocessors. Design trade-offs for microprogrammed control are discussed in the context of semiconductor design constraints which limit the size, speed, complexity and pin-out of circuits. Aspects of the control unit of a new generation microprocessor, which has a two level microprogrammed structure, are presented.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126092560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
A comparison of the code space and execution time required for FORTRAN assignment statements on six computer architectures 六种计算机体系结构上FORTRAN赋值语句所需代码空间和执行时间的比较
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804308
Richard A. Belgard, V. Schneider
{"title":"A comparison of the code space and execution time required for FORTRAN assignment statements on six computer architectures","authors":"Richard A. Belgard, V. Schneider","doi":"10.1145/1014198.804308","DOIUrl":"https://doi.org/10.1145/1014198.804308","url":null,"abstract":"A method is presented for deriving lower and upper bounds for memory space and execution time of compiled FORTRAN assignment statements. Formulas, in terms of variable references, are presented. The method is applied to six hypothetical computer architectures, standardized to eliminate variations resulting from addressing strategies and varying opcode lengths. The results are presented in tabular form.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125498497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Automatic synthesis of microcontrollers 自动合成微控制器
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804318
Andrew W. Nagle
{"title":"Automatic synthesis of microcontrollers","authors":"Andrew W. Nagle","doi":"10.1145/1014198.804318","DOIUrl":"https://doi.org/10.1145/1014198.804318","url":null,"abstract":"A method is proposed for automating the design of a microcontroller from a register transfer level description of a digital system. This method designs the format of the control word, determines the timing of branch decisions, and specifies the content of the microprogram. A data structure is introduced which supports some heuristic optimization of the design. The goal of the design method is to produce correct designs that are partially optimized with a practical amount of computing effort. An example is given to show how the method works.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126898087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
REDUCE/1700: A micro-coded Algebra system REDUCE/1700:一个微编码代数系统
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804322
M. Griss, R. Kessler
{"title":"REDUCE/1700: A micro-coded Algebra system","authors":"M. Griss, R. Kessler","doi":"10.1145/1014198.804322","DOIUrl":"https://doi.org/10.1145/1014198.804322","url":null,"abstract":"The status of an ongoing micro-coded Algebra machine project is reviewed. We have implemented a LISP “machine” on the Burroughs B1726 computer, capable of supporting the REDUCE Algebra system. A portable version of this LISP machine (written in a portable implementation language, BIL), can be used to produce a compact and efficient LISP or REDUCE for smaller machines (it also serves as a bootstrapping kernel for larger machines).\u0000 In this paper, we summarize the current status of the MBALM/1700 project, aimed at producing a micro-coded LISP and Algebra System on the Burroughs B1726 computer.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121422459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Firmware versus software verification 固件与软件验证
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804320
S. Budkowski, P. Dembinski
{"title":"Firmware versus software verification","authors":"S. Budkowski, P. Dembinski","doi":"10.1145/1014198.804320","DOIUrl":"https://doi.org/10.1145/1014198.804320","url":null,"abstract":"The paper presents an uniform framework in which the firmware verification problem can be reduced to the software one. It is shown how to transform the control memory (ROM) content into a microprogram written in the specially designed language MIDDLE and what kind of information has to be included in the hardware documentation in order to make the transformation possible. Once such a microprogram is found, different software methods of verification, outlined in the paper, can be applied.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116613668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Improving the performance of interpretive hierarchies by the introduction of local hardware 通过引入本地硬件来提高解释性层次结构的性能
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804300
M. Manthey
{"title":"Improving the performance of interpretive hierarchies by the introduction of local hardware","authors":"M. Manthey","doi":"10.1145/1014198.804300","DOIUrl":"https://doi.org/10.1145/1014198.804300","url":null,"abstract":"This paper introduces the notion of improving the performance of interpretive hierarchies by filtering out trivial operations at the highest possible level of the hierarchy and executing them by hardware local to that level. The technique can be used either with microprocessors or a set of identical general purpose hardware modules together with tables specifying the details of the specific interpreters.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"289 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132608273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Experience with an interactive basic machine implemented using the Burroughs B1700 使用Burroughs B1700实现交互式基本机器的经验
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804312
J. M. Hemphill, Richard T. Thomas
{"title":"Experience with an interactive basic machine implemented using the Burroughs B1700","authors":"J. M. Hemphill, Richard T. Thomas","doi":"10.1145/1014198.804312","DOIUrl":"https://doi.org/10.1145/1014198.804312","url":null,"abstract":"This paper describes the structure of the interpretive environment as designed and implemented and gives some comparisons of this system with another BASIC language interpreter. Some specific conclusions about the suitability of the B1700/1800 for this particular type of environment are given, along with some general conclusions regarding the interpretation process itself.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126405731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PASC-HLL: An experience in design techniques for firmware and the supporting hardware PASC-HLL:固件和支持硬件的设计技术经验
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804313
J. Schoellkopf
{"title":"PASC-HLL: An experience in design techniques for firmware and the supporting hardware","authors":"J. Schoellkopf","doi":"10.1145/1014198.804313","DOIUrl":"https://doi.org/10.1145/1014198.804313","url":null,"abstract":"PASC-HLL design started from a study of the high-level language PASCAL which allowed the definition of a special purpose intermediate language. A new mechanism for pipe-lined execution of polish strings using a FIFO queue instead of a push-down stack [1] made possible the design of a pipe-lined architecture bit-slice computer for high level language called PASC-HLL [2]. That computer consists in five special purpose microprogrammed processors, each being involved in a special function (instruction fetch, operand fetch, execution of operators, local storage management, and memory access).","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127417447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Levels of representation of programs and the architecture of universal host machines 程序的表示层次和通用主机的体系结构
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804311
B. R. Rau
{"title":"Levels of representation of programs and the architecture of universal host machines","authors":"B. R. Rau","doi":"10.1145/1014198.804311","DOIUrl":"https://doi.org/10.1145/1014198.804311","url":null,"abstract":"The issue of high level language support is treated in a systematic top-down manner. Program representations are categorized into three classes with respect to a host processor: high level representations, directly interpretable representations and directly executable representations. The space of intermediate languages for high level language support is explored and it is shown that whereas the ideal intermediate language from the point of view of execution time is a directly executable one, the best candidate from the viewpoint of memory requirements is a heavily encoded directly interpretable representation. The concept of dynamic translation is advanced as a means for achieving both goals simultaneously; the program is present in the memory in a compact static representation, but its working set is maintained in a dynamic representation which minimizes execution time. The architecture and organization of a universal host machine, incorporating this strategy, is outlined and the potential performance gains due to dynamic translation are studied.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114711528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Design of an emulator oriented microprogrammable computer 面向仿真器的微可编程计算机的设计
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804310
J. Soh, Ron Marko
{"title":"Design of an emulator oriented microprogrammable computer","authors":"J. Soh, Ron Marko","doi":"10.1145/1014198.804310","DOIUrl":"https://doi.org/10.1145/1014198.804310","url":null,"abstract":"This paper presents a design and implementation of a computer hardware for emulation using chip sliced microprocessors. The system has been built at Wright State University Computer Science Laboratory for instructional purposes. It provides an efficient interactive method for the execution of microcode in emulator development efforts. The system consists of two processing units, FAIRCHILD F-8 and INTEL 3000 bit slices, and two modules of RAM, one for the main memory having 8 bit words, the other for dynamic microprogram memory having 32 bit words.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128402025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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