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Proposal on efficient address allocation algorithm for horizontal microprograms 一种有效的横向微程序地址分配算法
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804305
Tadashi Tanaka, T. Kawada, T. Emori
{"title":"Proposal on efficient address allocation algorithm for horizontal microprograms","authors":"Tadashi Tanaka, T. Kawada, T. Emori","doi":"10.1145/1014198.804305","DOIUrl":"https://doi.org/10.1145/1014198.804305","url":null,"abstract":"A new algorithm to allocate horizontal microprograms having many addressing restrictions is presented in this note. This algorithm, using simultaneous partitioning, sufficiently maximizes the microprogram performance and minimizes the necessary memory amount in practical use.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124324146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A technique of global optimization of microprograms 微程序全局优化技术
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804306
M. Tokoro, T. Takizuka, E. Tamura, Ichirou Yamaura
{"title":"A technique of global optimization of microprograms","authors":"M. Tokoro, T. Takizuka, E. Tamura, Ichirou Yamaura","doi":"10.1145/1014198.804306","DOIUrl":"https://doi.org/10.1145/1014198.804306","url":null,"abstract":"This paper describes a technique of global optimization of microprograms including loops and recursive subroutines. This technique can be applied to a wide variety of microprogrammable machines. The principle of global optimization, four basic types of global optimization, and extended types of global optimization are discussed and the optimization algorithm is shown. Its effectiveness is evaluated and confirmed by applying it to an existing microprogrammable computer composed of LSI processor modules.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121068010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Design objectives for high level microprogramming languages 高级微程序设计语言的设计目标
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804325
K. Malik, T. Lewis
{"title":"Design objectives for high level microprogramming languages","authors":"K. Malik, T. Lewis","doi":"10.1145/1014198.804325","DOIUrl":"https://doi.org/10.1145/1014198.804325","url":null,"abstract":"The primitive operations of a high level language for producing emulators is shown to include special purpose features specific to virtual machine implementation. A Hierarchy of data types, short reliable language constructs, and control structures that minimize emulator complexity are suggested by a goal-directed, structured design methodology. In addition, structural “clues” generated by the language compiler assist in producing portable, yet efficient horizontal micro code for partially-encoded host architectures.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126176986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A methodology for programming a pipeline array processor 流水线阵列处理器的编程方法
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804314
D. Cohen
{"title":"A methodology for programming a pipeline array processor","authors":"D. Cohen","doi":"10.1145/1014198.804314","DOIUrl":"https://doi.org/10.1145/1014198.804314","url":null,"abstract":"In this note a recursive filter implementation is discussed, analyzed and programmed in the most efficient way for the FPS-AP120B array processor.\u0000 The purpose of this note is not only to demonstrate a good technique for programming this filter (even though it is a noble goal by itself), but to demonstrate the methodology involved.\u0000 The FPS-AP120B array processor was chosen because it has microprogrammed control parallel pipeline architecture, which is typical for a wide class of high performance array processors.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131911255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Our machine, a microcoded LSI processor 我们的机器，一个微编码的大规模集成电路处理器
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804298
D. Johannsen
{"title":"Our machine, a microcoded LSI processor","authors":"D. Johannsen","doi":"10.1145/1014198.804298","DOIUrl":"https://doi.org/10.1145/1014198.804298","url":null,"abstract":"Current LSI technology allows the systems designer to construct complex data processing structures containing tens of thousands of transistors on single silicon chips. Constraints imposed by the technology influence design tradeoffs and result in computer architectures dramatically different from the more classical computer designs. At CalTech we are exploring the possibilities offered by nMOS technology, with the “Our Machine” (OM) project being one of the current research projects. The OM project is investigating the structured design of a multi-chip microcoded processor system. Due to constraints imposed by limited man- and computer-power, we are gaining insights into future constraints that will be placed on all large chip designs as the technology improves to allow chips with hundreds of times the complexity of today's designs.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116187650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
On the packing of micro-operations into micro-instruction words 微操作的微指令字封装研究
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804307
G. Wood
{"title":"On the packing of micro-operations into micro-instruction words","authors":"G. Wood","doi":"10.1145/1014198.804307","DOIUrl":"https://doi.org/10.1145/1014198.804307","url":null,"abstract":"This paper discusses the problem of packing a serially expressed straight line segment of micro-program into micro-instruction words of a particular format. It outlines and compares the methods that have been proposed to solve particular instances of the problem and describes a program written to solve the general case.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127106376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Design considerations for a QM-1 based multimicroprocessor emulation system 基于QM-1的多微处理器仿真系统的设计考虑
MICRO 11 Pub Date : 1978-11-19 DOI: 10.1145/1014198.804309
S. Crocker
{"title":"Design considerations for a QM-1 based multimicroprocessor emulation system","authors":"S. Crocker","doi":"10.1145/1014198.804309","DOIUrl":"https://doi.org/10.1145/1014198.804309","url":null,"abstract":"Microprocessors, which are now readily available, are being used in the design of many systems. Soon avionic systems will be designed that use many microprocessors working together. Systems based on multiple microprocessors (MMP) will be designed to offer higher throughput and/or higher reliability than uniprocessor systems.\u0000 There are now very few design tools to aid in developing or evaluating proposed microprocessor systems. One highly useful tool is an emulation facility for modeling, testing, and measuring proposed MMP systems.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133162751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The LASS hardware processor LASS硬件处理器
MICRO 11 Pub Date : 1976-06-15 DOI: 10.1145/1014198.804302
P. Kunz, Richard N. Fall, M. Gravina, H. Brafman
{"title":"The LASS hardware processor","authors":"P. Kunz, Richard N. Fall, M. Gravina, H. Brafman","doi":"10.1145/1014198.804302","DOIUrl":"https://doi.org/10.1145/1014198.804302","url":null,"abstract":"The problems of data analysis with hardware processors are reviewed and a description is given for a programmable processor. This processor, the 168/E, has been designed for use in the LASS multi-processor system; it has an execution speed comparable to that of the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128224902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
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