{"title":"面向仿真器的微可编程计算机的设计","authors":"J. Soh, Ron Marko","doi":"10.1145/1014198.804310","DOIUrl":null,"url":null,"abstract":"This paper presents a design and implementation of a computer hardware for emulation using chip sliced microprocessors. The system has been built at Wright State University Computer Science Laboratory for instructional purposes. It provides an efficient interactive method for the execution of microcode in emulator development efforts. The system consists of two processing units, FAIRCHILD F-8 and INTEL 3000 bit slices, and two modules of RAM, one for the main memory having 8 bit words, the other for dynamic microprogram memory having 32 bit words.","PeriodicalId":336739,"journal":{"name":"MICRO 11","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1978-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of an emulator oriented microprogrammable computer\",\"authors\":\"J. Soh, Ron Marko\",\"doi\":\"10.1145/1014198.804310\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a design and implementation of a computer hardware for emulation using chip sliced microprocessors. The system has been built at Wright State University Computer Science Laboratory for instructional purposes. It provides an efficient interactive method for the execution of microcode in emulator development efforts. The system consists of two processing units, FAIRCHILD F-8 and INTEL 3000 bit slices, and two modules of RAM, one for the main memory having 8 bit words, the other for dynamic microprogram memory having 32 bit words.\",\"PeriodicalId\":336739,\"journal\":{\"name\":\"MICRO 11\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1978-11-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"MICRO 11\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1014198.804310\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"MICRO 11","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1014198.804310","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of an emulator oriented microprogrammable computer
This paper presents a design and implementation of a computer hardware for emulation using chip sliced microprocessors. The system has been built at Wright State University Computer Science Laboratory for instructional purposes. It provides an efficient interactive method for the execution of microcode in emulator development efforts. The system consists of two processing units, FAIRCHILD F-8 and INTEL 3000 bit slices, and two modules of RAM, one for the main memory having 8 bit words, the other for dynamic microprogram memory having 32 bit words.
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