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2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)最新文献

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An Environment for Design Space Exploration Using gem5-McPAT 基于gem5-McPAT的设计空间探索环境
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.042
Renan Tashiro, M. Oyamada
{"title":"An Environment for Design Space Exploration Using gem5-McPAT","authors":"Renan Tashiro, M. Oyamada","doi":"10.1109/SBESC.2016.042","DOIUrl":"https://doi.org/10.1109/SBESC.2016.042","url":null,"abstract":"Design space exploration of embedded systems is an example of a multiobjective problem. At System Level, different solutions can be generated using different mappings of hardware and software. To fulfill the requirements like cost, energy consumption, performance, and power, these different solutions must be evaluated. This work presents an environment for design space exploration aiming to estimate area, energy, performance and power of different solutions in a multicore architecture. To obtain these measures, the simulators gem5 and McPAT are used. They are integrated into the environment VIPEX (Virtual Platform Exploration), a visual framework focused on simplifying the process of design space exploration","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121589394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Distributed Platform for Integration of FPGA-based Embedded Systems 基于fpga的嵌入式系统分布式集成平台
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.021
Daniel C. Morais, T. W. Silva, T. Nascimento, E. Melcher, A. Brito
{"title":"A Distributed Platform for Integration of FPGA-based Embedded Systems","authors":"Daniel C. Morais, T. W. Silva, T. Nascimento, E. Melcher, A. Brito","doi":"10.1109/SBESC.2016.021","DOIUrl":"https://doi.org/10.1109/SBESC.2016.021","url":null,"abstract":"The challenge target by this work is to synchronize heterogeneous and distributed devices. For this purpose a middleware is presented as an infrastructure that facilitates sending and receiving messages among distributed and heterogeneous systems, called Virtual Bus. In order to improve the interoperabilty with legacy systems, it was developed using the IEEE 1516 standard (called HLA - High Level Architecture). As proof of concept experiment a version of MD5 (Message-Digest Algorithm 5) was implemented. This algorithm was processed in a PC, in FPGA and in an ARM processor, separately and joint in a unique environment integrated by Virtual Bus. The experiments demonstrated satisfactory results related to communication and performance.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127375508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Runtime Mapping Algorithm to Tolerate Permanent Faults in a CGRA 一种CGRA容错的运行时映射算法
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.018
A. Lopes, Eliselma Santos, M. Kreutz, M. Pereira
{"title":"A Runtime Mapping Algorithm to Tolerate Permanent Faults in a CGRA","authors":"A. Lopes, Eliselma Santos, M. Kreutz, M. Pereira","doi":"10.1109/SBESC.2016.018","DOIUrl":"https://doi.org/10.1109/SBESC.2016.018","url":null,"abstract":"This work proposes to combine a fast runtime mapping algorithm to a fault tolerance mechanism to tolerate permanent faults in a Coarse-Grained Reconfigurable Architecture. In order to provide fault tolerance, the runtime mapping algorithm isolates the faulty functional units and allocates the instructions only in the fault-free ones. Since the solution depends on the amount of functional units available and the fault rate, fault injection and mapping were simulated considering different fault rates and architecture size. The results demonstrate that even at fault rates over 50% in functional units, the runtime mapping algorithm was able to map instructions into the architecture in most of the tested applications. Additionally, the time for mapping instructions into the CGRA remained in order of microseconds","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126639088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Cache Design Assessment Approach for Embedded Real-Time Systems Based on Execution Time Measurement 基于执行时间测量的嵌入式实时系统缓存设计评估方法
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.033
D. Dias, George Lima, E. Barros
{"title":"A Cache Design Assessment Approach for Embedded Real-Time Systems Based on Execution Time Measurement","authors":"D. Dias, George Lima, E. Barros","doi":"10.1109/SBESC.2016.033","DOIUrl":"https://doi.org/10.1109/SBESC.2016.033","url":null,"abstract":"Due to the increasing complexity of embedded systems, simulation is of paramount importance during design phase. Often such systems must obey real-time constraints, calling for worst-case execution time assessment mechanisms. Although there is a wide range of simulation tools in the embedded systems domain, mechanisms for performing high abstraction level estimates for task execution times within a controlled environment are still needed. Non-determinism introduced by cache, multi-core and operating systems, for example, makes timing analysis highly complex or even impossible. We address this problem by presenting a RISC-V Instruction Set Simulation platform equipped with a task profiling mechanism for cache aware execution time measurements. The generated SystemC processor simulation model is integrated within a high abstraction level simulation platform with main memory and cache. Experimental results show that by making use of this kind of platform, designers can easily monitor task execution time as a function of measured code portion, cache sizes or cache policies employed helping in their decisions.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131719006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Framework for the Analysis of UAV Strategies Using Co-simulation 基于联合仿真的无人机策略分析框架
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.011
J. D. Barros, Thyago Oliveira, Vivek Nigam, A. Brito
{"title":"A Framework for the Analysis of UAV Strategies Using Co-simulation","authors":"J. D. Barros, Thyago Oliveira, Vivek Nigam, A. Brito","doi":"10.1109/SBESC.2016.011","DOIUrl":"https://doi.org/10.1109/SBESC.2016.011","url":null,"abstract":"Systems using Unmanned Aerial Vehicles (UAV) are typical examples of cyber-physical systems. Designing such systems is not a trivial task because it brings the challenge of dealing with the uncertainty that is inherent to this type of system. Therefore, it is necessary the usage of appropriate tools for design that can ensure implementation of these systems with a certain level of confiability. Thus, the purpose of this work is to integrate two simulators via HLA in order to simulate and evaluate different flights strategies. For this, it is presented a simulation environment that can execute flight plans in order to evaluate different strategies in uncertain scenarios. The simulator was developed in Ptolemy and integrated with SITL/ArduPilot via HLA. With the use of the approach presented in this paper it is possible to obtain results closer to reality, thus more efficient flight strategies can be developed and evaluate.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131126272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Reaching Optimum Solutions for the Low Power Hard Real-Time Task Allocation on Multiple Heterogeneous Processors Problem 多异构处理器低功耗硬实时任务分配问题的最优解
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.027
E. Valentin, Rosiane de Freitas, R. Barreto
{"title":"Reaching Optimum Solutions for the Low Power Hard Real-Time Task Allocation on Multiple Heterogeneous Processors Problem","authors":"E. Valentin, Rosiane de Freitas, R. Barreto","doi":"10.1109/SBESC.2016.027","DOIUrl":"https://doi.org/10.1109/SBESC.2016.027","url":null,"abstract":"The usage of heterogeneous multicore platforms is appealing for applications, e.g. hard real-time systems, due to the potential reduced energy consumption offered by such platforms. However, the power wall is still a barrier to improving the processor design process due to the power consumption of components. Hard real-time systems are part of life critical environments and reducing the energy consumption on such systems is an onerous and complex process. This paper assesses the problem of finding optimum allocations and frequency assignments of hard real-time tasks among heterogeneous processors targeting low power consumption but taking into account timing constraints. We also propose models based on a well-established formulation in the operational research literature of the Multilevel Generalized Assignment Problem (MGAP). We tackle the problem from the perspective of different integer programming mathematical formulations and their interplay on the search for optimal solutions for RM and EDF. Computational experiments show that providing upper bounds determined by a meta-heuristic based on genetic algorithm reduces the time to finding optimal solution from hours to milliseconds, enabling us to still pursue optimum in larger instances.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116352813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Embedding a Neural Classifier to Detect Faults in a Three-Phase Induction Motor 基于神经分类器的三相异步电动机故障检测
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.028
Renan Gomes Vieira, R. Cunha, Cláudio M. S. Medeiros, Elias Teodoro da Silva
{"title":"Embedding a Neural Classifier to Detect Faults in a Three-Phase Induction Motor","authors":"Renan Gomes Vieira, R. Cunha, Cláudio M. S. Medeiros, Elias Teodoro da Silva","doi":"10.1109/SBESC.2016.028","DOIUrl":"https://doi.org/10.1109/SBESC.2016.028","url":null,"abstract":"In the literature, a neural classifier design is usually evaluated using only a computer simulator. There is little discussion detailing the rest of the process until the very end step, when the embedded system is implemented. This work aims to fill this gap by analyzing the flow from a classifier, already designed and validated, to its implementation on an embedded platform with resource constraints. The classifier accuracy is evaluated when adopting different strategies to simplify data acquisition process, aiming to reduce resource usage in the target platform. To validate the approach, an implementation is made in a DSP microcontroller and the accuracy results are compared to that obtained by computational simulation.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114695406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Improving Network I/O Performance in Virtual Machines through Workload Profile Clustering 通过工作负载配置文件集群提高虚拟机的网络I/O性能
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.014
Stephany Zanchi Dionysio, L. Nacamura, C. Maziero
{"title":"Improving Network I/O Performance in Virtual Machines through Workload Profile Clustering","authors":"Stephany Zanchi Dionysio, L. Nacamura, C. Maziero","doi":"10.1109/SBESC.2016.014","DOIUrl":"https://doi.org/10.1109/SBESC.2016.014","url":null,"abstract":"The unpredictability of virtual machines workload makes effective CPU resources allocation a hard assignment for the hypervisor. Even if a virtual machine is allocated with adequate CPU resources, the quality of service of those running both CPU and I/O intensive tasks (heterogeneous workload), may be seriously affected if they are not provided in a timely manner. As server consolidation grows, CPU sharing among multiple virtual machines leads to negative impact on I/O intensive tasks running within the guest OS, due to incurred scheduling latency and lack of prioritization by hypervisor's scheduler. Although a fair amount of researches have dedicated to improve I/O performance on a multi-core platform through the implementation of coexisting schedulers, heterogeneous workloads still lacks of in-depth exploration. In this paper, we systematically evaluate scheduler's interference on I/O responsiveness of heterogeneous workloads domains under server consolidation. The performance study aims to create a synthetic heterogeneous workload based on media streaming applications by varying packet sizes. Furthermore, we apply the coexisting schedulers approach in order to analyze the linearity of quality of service metrics such as throughput, jitter and packet loss over this specific scenario.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115401018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Towards a Low-Cost Augmented Reality Head-Mounted Display with Real-Time Eye Center Location Capability 具有实时眼中心定位能力的低成本增强现实头戴式显示器
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.013
Thiago D'Angelo, S. Delabrida, Ricardo A. O. Oliveira, A. Loureiro
{"title":"Towards a Low-Cost Augmented Reality Head-Mounted Display with Real-Time Eye Center Location Capability","authors":"Thiago D'Angelo, S. Delabrida, Ricardo A. O. Oliveira, A. Loureiro","doi":"10.1109/SBESC.2016.013","DOIUrl":"https://doi.org/10.1109/SBESC.2016.013","url":null,"abstract":"The real-time detection of eye center location provides valuable information to be used in a wide range of applications such as face alignment, face recognition, human-computer interaction, device control for people with disabilities and user's attention detection. Gaze tracking systems is another type of application that uses the eye center location to infer the direction of the user's gaze. These systems can be applied to Augmented Reality (AR) Head-Mounted Displays (HMDs) in order to improve the User Experience. This work presents a low-cost AR HMD prototype with real-time eye center location capability. This work also presents an overview of Augmented Reality Head-Mounted Displays and methods for eye center location found in the literature. To assess our AR HMD prototype, we choose a state-of-the-art method for eye center location found in the literature and evaluate its real-time performance in different development boards.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131530855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
SMT-based Verification Applied to Non-convex Optimization Problems 基于smt的验证在非凸优化问题中的应用
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.010
Rodrigo F. Araujo, I. Bessa, L. Cordeiro, J. E. C. Filho
{"title":"SMT-based Verification Applied to Non-convex Optimization Problems","authors":"Rodrigo F. Araujo, I. Bessa, L. Cordeiro, J. E. C. Filho","doi":"10.1109/SBESC.2016.010","DOIUrl":"https://doi.org/10.1109/SBESC.2016.010","url":null,"abstract":"This paper presents a novel, complete, and flexible optimization algorithm, which relies on recursive executions that re-constrains a model-checking procedure based on Satisfiability Modulo Theories (SMT). This SMT-based optimization technique is able to optimize a wide range of functions, including non-linear and non-convex problems using fixed-point arithmetic. Although SMT-based optimization is not a new technique, this work is the pioneer in solving non-linear and non-convex problems based on SMT; previous applications are only able to solve integer and rational linear problems. The proposed SMT-based optimization algorithm is compared to other traditional optimization techniques. Experimental results show the efficiency and effectiveness of the proposed algorithm, which finds the optimal solution in all evaluated benchmarks, while traditional techniques are usually trapped by local minima.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"93 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120835501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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