2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)最新文献

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Design Space Exploration Using UTNoCs and Genetic Algorithm 利用utnoc和遗传算法设计空间探索
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.038
J. Mesquita, Marcos Oliveira da Cruz, M. Pereira, M. Kreutz
{"title":"Design Space Exploration Using UTNoCs and Genetic Algorithm","authors":"J. Mesquita, Marcos Oliveira da Cruz, M. Pereira, M. Kreutz","doi":"10.1109/SBESC.2016.038","DOIUrl":"https://doi.org/10.1109/SBESC.2016.038","url":null,"abstract":"During the design of multiprocessor architectures, the design space exploration step may be aided by tools that assist and accelerate this process. The project of architectures whose communications are based on Networks-on-Chip (NoCs), usually relies on regular topologies. Following another path, this work presents a high-level design space exploration tool aiming at generate optimized irregular NoC topologies. The solutions generated by the tool are called UTNoC, Undefined Topology Network-on-Chip. Taking as entry, communications behaviour modelled as traffic patterns and a set of communication routers, the tool searches for optimized ways to connect them, in order to improve performance and to reduce the total number of connections. The tool is based on evolutionary algorithms. Simulation results show improvements in reducing both the average latency and the number of connections, when compared to an equivalent Mesh topology.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131815145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Mobile Nodes as a Dynamic Management Strategy to Improve Coverage in Wireless Sensor Networks 移动节点作为一种提高无线传感器网络覆盖的动态管理策略
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.035
A. Gonzalez, P. Ferreira, L. Brisolara
{"title":"Mobile Nodes as a Dynamic Management Strategy to Improve Coverage in Wireless Sensor Networks","authors":"A. Gonzalez, P. Ferreira, L. Brisolara","doi":"10.1109/SBESC.2016.035","DOIUrl":"https://doi.org/10.1109/SBESC.2016.035","url":null,"abstract":"Inspired on the force fields theory of mobile robotics, this paper defines a simple method for event-triggered wireless sensor networks reorganization through the adoption of mobile sensor nodes. Following this dynamic management strategy nodes can move itself to maximize the area coverage avoiding sense on the same place. Through experiments, this work evaluates the proposed method with different network setups, varying adopted topology (random and mesh) as well as the network density, regarding the number of events sensed by day. Furthermore, we compare the adoption of the mobility against to the load balancing state-of-the-art techniques. In random networks configurations, dynamically reorganized mobile nodes increase the coverage in low density networks, increasing the number of sensed events in around 220%. As density is increased, mobile nodes sense around 2% more events in comparison to the static ones, minimizing the coverage limitation of random deployments and approximating its efficiency to the static nodes deployed in mesh.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127377072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Characterizing Interoperability in Context-Aware Software Systems 上下文感知软件系统的互操作性特征
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.039
R. Motta, K. Oliveira, G. Travassos
{"title":"Characterizing Interoperability in Context-Aware Software Systems","authors":"R. Motta, K. Oliveira, G. Travassos","doi":"10.1109/SBESC.2016.039","DOIUrl":"https://doi.org/10.1109/SBESC.2016.039","url":null,"abstract":"Context-awareness feature has been widely employed in the last years due to their usefulness to enhance systems functional reliability and user experience. Different software and hardware technologies can be integrated and used to capture context information, without user intervention. However, the heterogeneity of technology makes interoperability a great development challenge. Moreover, its evaluation for the context-aware system is also not trivial. Considering the relevance of the topic, we performed a characterization research (secondary study) aiming at revealing evidence on how interoperability has been addressed in context-aware software systems (CASS). Despite the observed conceptual divergence on interoperability, we present a set of evidence-based characteristics that can support decision-making and evaluation of interoperability on such systems. This work also introduces some research challenges aiming at to improve what we know about interoperability in CASS.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129266008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
The Integration of GPU-based and Heterogeneous Devices Using HLA 基于gpu和异构器件的HLA集成
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.032
Halamo G. R. Andrade, Daniel C. Morais, T. W. Silva, T. Nascimento, A. Brito
{"title":"The Integration of GPU-based and Heterogeneous Devices Using HLA","authors":"Halamo G. R. Andrade, Daniel C. Morais, T. W. Silva, T. Nascimento, A. Brito","doi":"10.1109/SBESC.2016.032","DOIUrl":"https://doi.org/10.1109/SBESC.2016.032","url":null,"abstract":"The use of distributed components may offer many advantages in the most types of applications. It includes, for example, the easy use of disperse resources in a network, allowing a potential gain on the processing power and data loading. But, the major challenge is interoperability and communication management. In this aspect, the High Level Architecture (HLA) establishes specific policies for data exchanging and time management of communication in the integration of the simulation components. Thus, this paper aims to explain and analyse the feasibility to integrate devices based on heterogeneous architectures using distributed and parallel computing, multi-core CPU and GPU, with OpenCL technology. For that, the use of the IEEE 1516 standard, called High Level Architecture, is proposed targeting this integration and allowing the use of all computing power from available devices in a distributed system. In this study experiments also were done to demonstrate the approach of running a simple parallel image processing application under the conceived architecture.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115827927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Embedded Nonlinear Model Predictive Formation Controller for Low-Cost Architectures 一种用于低成本结构的嵌入式非线性模型预测编队控制器
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.041
Diego Sousa, T. Nascimento, A. Brito
{"title":"An Embedded Nonlinear Model Predictive Formation Controller for Low-Cost Architectures","authors":"Diego Sousa, T. Nascimento, A. Brito","doi":"10.1109/SBESC.2016.041","DOIUrl":"https://doi.org/10.1109/SBESC.2016.041","url":null,"abstract":"The purpose of this study is to adapt and embed a navigation system and control mobile robots, based on nonlinear model predictive formation control (NMPFC), in a low-cost commercially available board. The system must provide sufficient computational resources so that the robot is able to converge, without losing performance, using the same prediction and control horizons applied in a laptop. The obtained results demonstrate that it is possible to use low-cost boards applying the embedded navigation and control system of mobile robots into the proposed scenario, using the same predictive and control horizons applied in a laptop.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126356673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the Impact of Dynamic Routing Metrics on a Geographic Protocol for WSNs 动态路由度量对无线传感器网络地理协议的影响
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.024
Davi Resner, G. Araújo, A. A. Fröhlich
{"title":"On the Impact of Dynamic Routing Metrics on a Geographic Protocol for WSNs","authors":"Davi Resner, G. Araújo, A. A. Fröhlich","doi":"10.1109/SBESC.2016.024","DOIUrl":"https://doi.org/10.1109/SBESC.2016.024","url":null,"abstract":"Message routing is a keystone of Wireless Sensor Networks (WSN). In many routing algorithms, sensor nodes forward data in a multicast fashion and a specific routing metric defines which of the receiving nodes is the next forwarder. If this metric is static, optimal routes tend to be overused and nodes in that route die quickly. The Trustful Space-Time Protocol (TSTP) is a cross-layer protocol designed to deliver authenticated, encrypted, timed, and georeferenced messages containing SI-compliant data in a resource-efficient way. It defines a novel, data-centric paradigm for programming WSNs and the IoT. In this paper, we discuss and evaluate dynamic routing in TSTP, which can explore routing metrics naturally given by the protocol's cross-layer, geo-oriented design, such as distance to the destination and message TTL (Time-to-Live). We introduce the idea of spatial distortion to map virtually any metric into a time-to-transmit offset, and evaluate the impact of different combinations of metrics. We assess the spatial distortion metrics on a TSTP implementation over IEEE 802.15.4 on the OMNET++ simulator, comparing their impact on the network in terms of end-to-end delay, fairness index, and delivery ratio.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123528619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Towards a Metamodel for a Requirements Engineering Process of Embedded Systems 嵌入式系统需求工程过程的元模型研究
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.022
Tarcísio Pereira, Deivson Albuquerque, Aêda Sousa, F. Alencar, J. Castro
{"title":"Towards a Metamodel for a Requirements Engineering Process of Embedded Systems","authors":"Tarcísio Pereira, Deivson Albuquerque, Aêda Sousa, F. Alencar, J. Castro","doi":"10.1109/SBESC.2016.022","DOIUrl":"https://doi.org/10.1109/SBESC.2016.022","url":null,"abstract":"In the embedded systems (ES) area, more than 50% of problems occur at system delivery and are related to misconceptions in capturing requirements. According to our systematic literature review (SLR), no evidence explicitly depicts how an embedded system must be elicited and specified. However, understanding the embedded systems and their environment is a strenuous activity. Even though current approaches present some contributions, the definition of a systematic requirements engineering process remains a challenging issue. Based on this shortcoming, we developed a metamodel that defines concepts and relationships that must be taken into account the development of an ES. From the metamodel, we define a precise requirements engineering process. This research presents the main results of a SLR, a resource model, and a sketch of a process to guide the requirements development of embedded systems.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114881080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Cryptographic API for Embedded Applications 嵌入式应用的加密API
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.034
Felipe Michels Fontoura, C. Maziero, M. A. Wehrmeister
{"title":"Cryptographic API for Embedded Applications","authors":"Felipe Michels Fontoura, C. Maziero, M. A. Wehrmeister","doi":"10.1109/SBESC.2016.034","DOIUrl":"https://doi.org/10.1109/SBESC.2016.034","url":null,"abstract":"This paper presents GEmSysC, an unified cryptographic API for embedded systems. Software layers implementing this API can be built over existing libraries, allowing embedded software to access cryptographic functions in a consistent way that does not depend on the underlying library. The API complies to good practices for API design and good practices for embedded software development and took its inspiration from other cryptographic libraries and standards. The main inspiration for creating GEmSysC was the CMSIS-RTOS standard, which defines an unified API for embedded software in a implementation-independent way, but targets operating systems instead of cryptographic functions. GEmSysC is made of a generic core and attachable modules, one for each cryptographic algorithm. Until now, three modules were been fully specified: AES, RSA, and SHA-256. As a proof of concept, two implementations of GEmSysC were made. One of them was built over wolfSSL, which is an open source library for embedded systems. The other was built over OpenSSL, which is open source and a de facto standard. Unlike wolfSSL, OpenSSL does not specifically target embedded systems. This paper displays test results showing GEmSysC to be simpler than other libraries in some aspects. These results have shown that both implementations incur in little overhead in computation time compared to the cryptographic libraries themselves. The overhead of the implementation has been measured for each cryptographic algorithm and is between around 0% and 0.17% for the implementation over wolfSSL and between 0.03% and 1.40% for the one over OpenSSL. This document also presents the memory costs for each implementation.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121977829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mutant Components: Efficiently Managing Multiple Implementations 突变组件:有效管理多个实现
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.023
João Gabriel Reis, A. A. Fröhlich
{"title":"Mutant Components: Efficiently Managing Multiple Implementations","authors":"João Gabriel Reis, A. A. Fröhlich","doi":"10.1109/SBESC.2016.023","DOIUrl":"https://doi.org/10.1109/SBESC.2016.023","url":null,"abstract":"The development of embedded system applications is driven by the usage of models of computation and their interaction with the underlying programming language and the interfaces of system components. Behind each interface there is a series of software and hardware operations with different shapes according to the availability of implementations, hardware accelerators, or processor cores, and the environmental conditions faced by the embedded system such as the power consumption or even the chip's temperature. For example, when running out of battery, a mobile device can decide to reconfigure the implementation of critical components for one that consumes less energy by delivering a functionality with a lower quality-of-service without depleting the battery. To cope with such adaptive systems without breaking the interface each component provide to the application, we propose a framework for mutant components whose implementation can be reconfigured during runtime. The system synthesis delivers a tailored wrapper for each component according to the number of implementations it has. We evaluate our proposal by profiling the execution time of methods from three components (AES, ADPCM, and DTMF) with a hardware and a software implementation to evaluate the overhead incurred to the resulting architecture regarding its the execution time.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130707613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluation of TDMA Robustness in WirelessHART Networks 无线shart网络中TDMA鲁棒性的评估
2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Pub Date : 2016-11-01 DOI: 10.1109/SBESC.2016.040
J. Winter, C. Pereira, J. Netto, Fernando A. Souza, C. M. D. Costa, I. Müller
{"title":"Evaluation of TDMA Robustness in WirelessHART Networks","authors":"J. Winter, C. Pereira, J. Netto, Fernando A. Souza, C. M. D. Costa, I. Müller","doi":"10.1109/SBESC.2016.040","DOIUrl":"https://doi.org/10.1109/SBESC.2016.040","url":null,"abstract":"Industrial wireless sensor networks are the next step in fieldbuses. In order to cope with harsh industrial environments, they must employ several mechanisms to increase reliability, to be comparable with cable-based networks. One of these mechanisms makes is the time division multiplexing as a medium access controller on data link layer, which prevents collisions within the network itself and provides real time communications. However, the use of such control mechanism implies on precise clock generation and maintenance, for the field devices to keep track of synchronized time slots. This paper presents a study related to clock source tolerances on WirelessHART protocol. A case study is conducted with a developed and certified WirelessHART field device, whose clock generator is depicted for the study. A fault condition in the clock generation for time division multiple access is created and tested within a topology controlled network. The results and conclusions revealed a possible catastrophic failure due to a faulty time source field device.","PeriodicalId":336703,"journal":{"name":"2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131054261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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