2022 IEEE European Test Symposium (ETS)最新文献_第5页

An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip 针对汽车片上系统嵌入式存储器互连逻辑的优化老化应力流

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810396

F. Angione, P. Bernardi, G. Filipponi, M. Reorda, D. Appello, V. Tancorre, R. Ugioli

{"title":"An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip","authors":"F. Angione, P. Bernardi, G. Filipponi, M. Reorda, D. Appello, V. Tancorre, R. Ugioli","doi":"10.1109/ETS54262.2022.9810396","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810396","url":null,"abstract":"The complexity of automotive Systems-on-a-Chip (SoCs) has enormously grown in the last decades. Today’s automotive SoCs are compelling due to technology improvements, different integration technologies, increased heterogeneity, and many available embedded memories. On balance, despite testing techniques that have been refined through years, traditional structural test methods, like scan and BIST, can cover a vast but not complete spectrum of all the possible defects. It appears that the divide-and-conquer approach founded on structural techniques may not be enough to reach every single element or to effectively stimulate the faulty behaviors that may show up during the lifetime of the device. Burn-In is widely used to reduce Infant Mortality, accelerating the evolution of weak points into defects via externally or internally induced stress.In this work, we focus on internal stress and present a generation strategy intended to automatically produce functional stress procedures for the Burn-In phase that exacerbate possible weak points which are likely to escape activation by structural tests, such that they more easily outbreak during the successive final test procedures. The proposed generation strategy primarily addresses the interconnections to embedded memories, which look challenging to stress by structural methods, including Logic and Memory BIST, and critical due to the integration of different technologies (i.e., logic gates and memory layout). In the considered test case, the proposed approach increases the average toggle activity by orders of magnitude with respect to Memory BIST. Furthermore, it provides a uniform distributed toggling activity.Results collected on an automotive SoC show how the stress provided by functional programs compares with the stress level provided by structural test methods measured in terms of toggling activity. The SpeedUp produced by the proposed procedure is 3.14X wrt to the MBIST executing the March C-algorithm.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125708274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On-Chip Training of Crosstalk Predictors to Fit Uncertainties 片上训练拟合不确定性的相声预测器

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810362

Rezgar Sadeghi, E. Akbari, Mohamad Ali Saber

引用次数: 0

Prediction of Thermally Accelerated Aging Process at 28nm 28nm热加速老化过程的预测

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810415

Parvez Chanawala, Ian Hill, S. Sheikholeslam, A. Ivanov

引用次数: 0

On Extracting Reliability Information from Speed Binning 从速度分组中提取可靠性信息的研究

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810443

Zahra Paria Najafi-Haghi, F. Klemme, H. Amrouch, H. Wunderlich

{"title":"On Extracting Reliability Information from Speed Binning","authors":"Zahra Paria Najafi-Haghi, F. Klemme, H. Amrouch, H. Wunderlich","doi":"10.1109/ETS54262.2022.9810443","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810443","url":null,"abstract":"Adaptive Voltage Frequency Scaling (AVFS) is an important means to overcome process-induced variability challenges for advanced high-performance circuits. AVFS requires and allows determining the maximum speed Fmax(Vdd) reachable under a set of certain operation voltages Vdd. In this paper, it is shown that the Fmax(Vdd) measurements contain relevant data to identify some hidden defects in a chip which are reliability threats and can cause device failures, but pass the speed binning procedure within the given specifications.Static Timing Analysis (STA) is applied to a circuit designed by using standard cell libraries in which the underlying transistors along with process variations have been carefully calibrated against industrial 14nm FinFET measurement data, and in-stances with and without injected small resistive open defects are generated. From the slope of the function Fmax(Vdd), a machine learning procedure can identify some defects with high precision and few false positives. These chips can be then discarded without any further need and cost for testing. It has to be noted that this reliability information comes for free from the data which is already generated, and does not need any additional measurements.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127923153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

FPGA Design Deobfuscation by Iterative LUT Modifications at Bitstream Level 位流级迭代LUT修改的FPGA设计去混淆

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1007/s41635-022-00130-y

M. Moraitis, E. Dubrova

引用次数: 1

PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory 基于RRAM和stt - mram的内存逻辑计算的PVT分析

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810436

M. Fieback, Christopher Münch, A. Gebregiorgis, G. Medeiros, M. Taouil, S. Hamdioui, M. Tahoori

{"title":"PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory","authors":"M. Fieback, Christopher Münch, A. Gebregiorgis, G. Medeiros, M. Taouil, S. Hamdioui, M. Tahoori","doi":"10.1109/ETS54262.2022.9810436","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810436","url":null,"abstract":"Emerging non-volatile resistive memories like Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) and Resistive RAM (RRAM) are in the focus of today’s research. They offer promising alternative computing architectures such as computation-in-memory (CiM) to reduce the transfer overhead between CPU and memory, usually referred to as the memory wall, which is present in all von Neumann architectures. A multitude of architectures with CiM capabilities are based on these devices, due to their inherent resistive behavior and thus their ability to perform calculation directly within the memory, and thus without invoking the CPU at all. However, emerging memories are sensitive to Process, Voltage and Temperature (PVT) variations. This sensitivity has an even larger impact on CiM architectures. In this paper, we analyze and compare the impact of PVT variations on STT-MRAM and RRAM-based CiM architectures. We perform a sensitivity analysis to identify which parts of the CiM structure are most susceptible to PVT variations, for each technology. Based on these analyses, we recommend that STT-MRAM is used in high-performance CiM, while RRAM is used for edge CiM.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133267559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

CNN-based Data-Model Co-Design for Efficient Test-termination Prediction 基于cnn的有效测试终止预测数据模型协同设计

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810406

Hongfei Wang, Zhanfei Wu, Wei Liu

{"title":"CNN-based Data-Model Co-Design for Efficient Test-termination Prediction","authors":"Hongfei Wang, Zhanfei Wu, Wei Liu","doi":"10.1109/ETS54262.2022.9810406","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810406","url":null,"abstract":"Failure diagnosis is a software-based data-driven procedure. Collecting an excessive amount of fail data not only increases the overall test cost, but may also lead to degradation of diagnostic resolution. Test-termination prediction is thus proposed to dynamically determine which failing test pattern to terminate testing, producing an amount of test data that is sufficient for an accurate diagnosis analysis. In this work, we describe a novel data-model co-design method of using deep learning method for efficient test-termination prediction. In particular, images describing the failing test responses are constructed from failure-log files. A multi-layer convolutional neural network (CNN) embedding a residual block is then trained, based on the images and known diagnosis results. The learned CNN model is later deployed in a test flow to determine the optimal test-termination for an efficient and quality diagnosis. Experiments on actual failing chips and standard benchmarks demonstrate that the proposed method outperforms SOTA works. Our method creates opportunities to harness the power of deep learning for improving diagnostic efficiency and quality.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133003570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimized diagnostic strategy for embedded memories of Automotive Systems-on-Chip 汽车片上系统嵌入式存储器的优化诊断策略

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810445

P. Bernardi, Giorgio Insinga, G. Paganini, R. Cantoro, P. Beer, M. Coppetta, N. Mautone, G. Carnevale, P. Scaramuzza, R. Ullmann

{"title":"Optimized diagnostic strategy for embedded memories of Automotive Systems-on-Chip","authors":"P. Bernardi, Giorgio Insinga, G. Paganini, R. Cantoro, P. Beer, M. Coppetta, N. Mautone, G. Carnevale, P. Scaramuzza, R. Ullmann","doi":"10.1109/ETS54262.2022.9810445","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810445","url":null,"abstract":"Embedded memories in Automotive Systems-on-Chip usually occupy a large die area portion. Consequently, their defectivity can strongly impact production yield for any automotive device. Along with the technology ramp-up phase and for statistical process control reasons during volume production, it is a good automotive industry practice to collect diagnostic information in addition to pure testing data. Designers and technology experts must receive accurate diagnostic results from failing devices to react to misbehavior by identifying and correcting the related issues at their source and drawing correct repair strategy conclusions. A commonly used approach resorts to the generation of failure bitmaps based on collecting all failing bits coordinates to be sent one by one to the tester. More efficiently, the encountered faults can be compacted or compressed in on-chip memory resources to be retrieved by the tester at the end of the memory test.This paper presents an on-chip method to compact diagnostic information during embedded memory testing. More specifically, the method is applied to diagnose embedded FLASH memories. This strategy permits the reconstruction of failure bitmaps without any loss, while compression approaches obtain an approximation. The proposed method uses a fraction of the memory requested by a coordinate-based bit mapping approach and is comparable to compression methods. At the cost of a moderate test time overhead, the proposed strategy permits dramatically increasing the number of devices that can be fully diagnosed without any bitmap reconstruction loss. Most failing devices in a real embedded FLASH production scenario were diagnosed after a single transfer from on-chip to the tester host computer.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132321414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

WLAN Rx PER Test Implementation in ATE 无线局域网Rx PER测试在ATE中的实现

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ETS54262.2022.9810366

Alban Haynse Immanuel, Jeyendran Nithyanadam

引用次数: 0

DFX: Exploring the Design Space for Quality DFX:为质量探索设计空间

2022 IEEE European Test Symposium (ETS) Pub Date : 2022-05-23 DOI: 10.1109/ets54262.2022.9810381

引用次数: 0