2016 16th International Conference on Application of Concurrency to System Design (ACSD)最新文献

Products of Transition Systems and Additions of Petri Nets 过渡系统的积与Petri网的补充

2016 16th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2016-06-22 DOI: 10.1109/ACSD.2016.10

Raymond R. Devillers

引用次数: 9

Utilizing Petri Nets for Teaching in Practical Courses on Collaborative Software Engineering Petri网在协同软件工程实践课程教学中的应用

2016 16th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2016-06-19 DOI: 10.1109/ACSD.2016.21

Dennis Schmitz, D. Moldt, Lawrence Cabac, David Mosteller, Michael Haustermann

{"title":"Utilizing Petri Nets for Teaching in Practical Courses on Collaborative Software Engineering","authors":"Dennis Schmitz, D. Moldt, Lawrence Cabac, David Mosteller, Michael Haustermann","doi":"10.1109/ACSD.2016.21","DOIUrl":"https://doi.org/10.1109/ACSD.2016.21","url":null,"abstract":"Teaching the application of Petri nets to software development is a major challenge for the Petri net community. We face this during our practical courses in that we teach the Paose-approach. Students need to get acquainted with the development tools. At the beginning of each course, we start with an introduction phase, which is followed by an intensification phase. In order to support the teachers as well as the students, we use explicated process models to restructure and augment the worksheets. The resulting worksheets enable the students to follow the structure of the processes step by step. In the last two projects, we already applied the restructured and augmented worksheets. We noticed that the students were able to process the worksheets more independently and were less confused and frustrated. In general this lead to a more relaxed teaching atmosphere. In this contribution we provide detailed insights into the teaching approach. We demonstrate our current best practices for teaching Petri nets in practical settings. In this regard, we describe how Petri nets can be utilized to improve learning materials (e.g. worksheets) and to this end, the effects of our restructured and augmented learning materials are evaluated.","PeriodicalId":334903,"journal":{"name":"2016 16th International Conference on Application of Concurrency to System Design (ACSD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121821160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

The Congruences below Fair Testing with Initial Stability 具有初始稳定性的公平检验下的同余

2016 16th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2016-06-19 DOI: 10.1109/ACSD.2016.15

A. Valmari

引用次数: 3

Checking Metric Temporal Logic with TRACE 用TRACE检查度量时间逻辑

2016 16th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2016-06-19 DOI: 10.1109/ACSD.2016.13

M. Hendriks, M. Geilen, A. Behrouzian, T. Basten, Hadi Alizadeh Ara, Dip Goswami

引用次数: 5

An Approach to Verification of MPI Applications Defined in a High-Level Model 高级模型中定义的MPI应用程序的验证方法

2016 16th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2016-06-19 DOI: 10.1109/ACSD.2016.17

Ondrej Meca, Stanislav Böhm, M. Behálek, P. Jančar

{"title":"An Approach to Verification of MPI Applications Defined in a High-Level Model","authors":"Ondrej Meca, Stanislav Böhm, M. Behálek, P. Jančar","doi":"10.1109/ACSD.2016.17","DOIUrl":"https://doi.org/10.1109/ACSD.2016.17","url":null,"abstract":"Kaira is a prototyping tool for developing MPI programs (Bohm et al., Petri Nets 2014). The user of Kaira suggests a parallelization of a given sequential C++ code by creating a visual Petri-net based model, the tool then automatically generates the corresponding stand-alone MPI application. One of the tool modules enables to verify that the suggested parallelization has not introduced unexpected behaviors caused by unintended orders of communications among processes. The verification uses a state-space exploration procedure. Here we report on a new substantial enhancement of this procedure, leading to a significant reduction of the explored state space. The enhancement is based on the well-known methods of stubborn sets and ample sets, and is tailored to the use in the above mentioned visual model. Our concrete method is particularly simple but the experiments show that it works very well for practical examples from the area of scientific computing in distributed environment. The experiments also confirm that the Kaira model together with this method outperforms other tools for verifying MPI programs (w.r.t. instance-size/time).","PeriodicalId":334903,"journal":{"name":"2016 16th International Conference on Application of Concurrency to System Design (ACSD)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126446513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Controlling Actions and Time in Parametric Timed Automata 参数定时自动机中的控制动作和时间

2016 16th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2016-06-01 DOI: 10.1109/ACSD.2016.20

É. André, M. Knapik, W. Penczek, L. Petrucci

引用次数: 6

From Petri Nets with Shared Variables to ITL 从共享变量Petri网到ITL

2016 16th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2016-06-01 DOI: 10.1109/ACSD.2016.12

Hanna Klaudel, M. Koutny, B. Moszkowski

{"title":"From Petri Nets with Shared Variables to ITL","authors":"Hanna Klaudel, M. Koutny, B. Moszkowski","doi":"10.1109/ACSD.2016.12","DOIUrl":"https://doi.org/10.1109/ACSD.2016.12","url":null,"abstract":"Petri nets and Interval Temporal Logic (ITL) are two formalisms for the specification and analysis of concurrent computing systems. Petri nets allow for a direct expression of causality aspects in system behaviour and in particular support system verification based on partial order reductions or invariant-based techniques. ITL, on the other hand, supports system verification by proving that the formula describing a system implies the formula describing a correctness requirement. It would therefore be desirable to establish a strong semantical link between these two models, thus allowing one to apply diverse analytical methods and techniques to a given system design. We have recently proposed such a semantical link between the propositional version of ITL (PITL) and Box Algebra (BA), which is a compositional model of basic (low-level) Petri nets supporting handshake action synchronisation between concurrent processes. In this paper, we extend this result by considering a compositional model of (high-level) Petri nets where concurrent processes communicate through shared variables. The main result is a method for translating a design expressed using a high-level Petri net into a semantically equivalent ITL formula.","PeriodicalId":334903,"journal":{"name":"2016 16th International Conference on Application of Concurrency to System Design (ACSD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124200195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Power-Normalized Performance Optimization of Concurrent Many-Core Applications 并发多核应用程序的功率标准化性能优化

2016 16th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2016-06-01 DOI: 10.1109/ACSD.2016.14

M. Travers, R. Shafik, Fei Xia

{"title":"Power-Normalized Performance Optimization of Concurrent Many-Core Applications","authors":"M. Travers, R. Shafik, Fei Xia","doi":"10.1109/ACSD.2016.14","DOIUrl":"https://doi.org/10.1109/ACSD.2016.14","url":null,"abstract":"Modern operating systems, such as Linux, are capable of executing multiple parallel applications concurrently on many-core platforms. Different applications may have different characteristics with regard to how they exercise the computation and memory resources in these platforms. This paper aims to investigate the impact of such differences on the overall energy consumption and performance tradeoffs. To analyze these tradeoffs, three PARSEC benchmark applications are chosen with different characteristics - memory-intensive, CPU-intensive and a mixture of both. These applications are then concurrently executed in various combinations in experiments, which also help establish optimized run-time controls in terms of dynamic voltage/frequency scaling (DVFS) and thread-to-core allocations at run-time. Such controls are based on state-space models derived through linear regression using the feedback from hardware performance counters. Using the benchmark applications, we demonstrate the effectiveness of our proposed method, which shows up to 23% improvement in power normalized performance expressed as the ratio between instructions per second (IPS) and power consumption (Watt).","PeriodicalId":334903,"journal":{"name":"2016 16th International Conference on Application of Concurrency to System Design (ACSD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122303132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Power and Energy Normalized Speedup Models for Heterogeneous Many Core Computing 异构多核计算的功率和能量归一化加速模型

2016 16th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2016-06-01 DOI: 10.1109/ACSD.2016.16

M. A. N. Al-hayanni, A. Rafiev, R. Shafik, F. Xia

{"title":"Power and Energy Normalized Speedup Models for Heterogeneous Many Core Computing","authors":"M. A. N. Al-hayanni, A. Rafiev, R. Shafik, F. Xia","doi":"10.1109/ACSD.2016.16","DOIUrl":"https://doi.org/10.1109/ACSD.2016.16","url":null,"abstract":"Continued technology scaling in VLSI has enabled more and more computation cores to be integrated in the same chip. This has facilitated the parallelization of processing and the increase of performance whilst keeping energy consumption at reasonable levels. To study the potential improvement of performance in such many core systems, three existing models have been popular in both the research community and industry. Amdahl's law is the original speedup model that estimates the maximum performance improvement with fixed workloads. Gustafson's law is a popular model that introduces variable workloads and estimates fixed time speedup. Sun and Ni combined the above two models into one considering the memory-bounded situation. These models are further extended via the Hill-Marty model to cover a limited form of heterogeneity. This paper extends these models to cover a more comprehensive assumption of core heterogeneity. We also present power and energy models based on the extended heterogeneous models. Our models cover popular power and performance control methods such as Dynamic Voltage Frequency Scaling (DVFS), power gating, etc. A case study is performed with an ARM big.LITTLE architecture containing Cortex A7 and A15 cores, including a comprehensive analysis with different ratios of parallel and sequential workloads to identify the most energy-efficient system configuration based on these models. Experimental results demonstrated high correlations between practically measured power normalized performance and that of the proposed extended models.","PeriodicalId":334903,"journal":{"name":"2016 16th International Conference on Application of Concurrency to System Design (ACSD)","volume":"1997 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128217040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Asynchronous Dataflow De-Elastisation for Efficient Heterogeneous Synthesis 高效异构合成的异步数据流反弹性

2016 16th International Conference on Application of Concurrency to System Design (ACSD) Pub Date : 2016-06-01 DOI: 10.1109/ACSD.2016.22

M. Mamaghani, D. Sokolov, J. Garside

{"title":"Asynchronous Dataflow De-Elastisation for Efficient Heterogeneous Synthesis","authors":"M. Mamaghani, D. Sokolov, J. Garside","doi":"10.1109/ACSD.2016.22","DOIUrl":"https://doi.org/10.1109/ACSD.2016.22","url":null,"abstract":"Algorithmic synthesis provides flexibility in design space exploration and improves design productivity by separating the concerns of system timing and functionality. This enables a designer to cope with the rapid increase of SoC complexity and to employ different computation and communication models with various timing constraints. De-elastisation emerged as a technique that transforms timing-free concurrent dataflow models to synchronous circuits while offering selective timing flexibility in the design. We adopt De-elastisation in an in-house EDA flow: it starts from a system specification in the Balsa language and uses eTeak to generate an elastic network of macro-modules. Based on structural analysis of the obtained network some of its portions are selectively transformed into synchronous circuits, in a supervised fashion, targeting better power and performance in the computation domain, whilst preserving fine-grained elasticity between communicating modules to handle timing uncertainties. We evaluate De-elastisation and compare it against some popular high-level synthesis technologies, namely LegUp, Bluespec, Chisel and Balsa using a set of benchmarks from the domain of Database Management Systems (DBMS) accelerators. Our experiments demonstrate the efficacy of Dataflow Decomposition and De-elastisation on the selected range of applications and its advantages in exploring the design trade-offs: a twofold increase in performance and 15% decrease in power consumption can be achievable at the expense of moderate area overhead.","PeriodicalId":334903,"journal":{"name":"2016 16th International Conference on Application of Concurrency to System Design (ACSD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124850560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2