Asynchronous Dataflow De-Elastisation for Efficient Heterogeneous Synthesis

Algorithmic synthesis provides flexibility in design space exploration and improves design productivity by separating the concerns of system timing and functionality. This enables a designer to cope with the rapid increase of SoC complexity and to employ different computation and communication models with various timing constraints. De-elastisation emerged as a technique that transforms timing-free concurrent dataflow models to synchronous circuits while offering selective timing flexibility in the design. We adopt De-elastisation in an in-house EDA flow: it starts from a system specification in the Balsa language and uses eTeak to generate an elastic network of macro-modules. Based on structural analysis of the obtained network some of its portions are selectively transformed into synchronous circuits, in a supervised fashion, targeting better power and performance in the computation domain, whilst preserving fine-grained elasticity between communicating modules to handle timing uncertainties. We evaluate De-elastisation and compare it against some popular high-level synthesis technologies, namely LegUp, Bluespec, Chisel and Balsa using a set of benchmarks from the domain of Database Management Systems (DBMS) accelerators. Our experiments demonstrate the efficacy of Dataflow Decomposition and De-elastisation on the selected range of applications and its advantages in exploring the design trade-offs: a twofold increase in performance and 15% decrease in power consumption can be achievable at the expense of moderate area overhead.