Proceedings IEEE Southeastcon '95. Visualize the Future最新文献_第5页

Fault tolerant token ring model development 容错令牌环模型开发

Proceedings IEEE Southeastcon '95. Visualize the Future Pub Date : 1995-03-26 DOI: 10.1109/SECON.1995.513070

T. Gilbar, S. Wunnava

{"title":"Fault tolerant token ring model development","authors":"T. Gilbar, S. Wunnava","doi":"10.1109/SECON.1995.513070","DOIUrl":"https://doi.org/10.1109/SECON.1995.513070","url":null,"abstract":"The token ring is one of the most popular local area network (LAN) schemes, and is very widely used. One of the major weaknesses of the token ring network is that if a single station fails, the entire network and the system is likely to fail. Also, with the distributed and concurrent processing schemes becoming increasingly popular, there is an ever growing need to interconnect several LANs for an integrated wide area network. Often, the protocols of the LAN and the protocols of the inter-connectivity are distinctly separate. This requires protocol conversions, additional hardware and software modules, which increase the delay of transmission and make the system less reliable. The authors have devised a methodology to minimize the bit faults in intercommunications. Frame formats of the emerging interconnection technology such as integrated services digital network (ISDN) using the existing telephone network are integrated with those of the conventional token ring protocols, in order to improve the fault tolerance of a token ring network, and make the interconnection of several token ring networks very simple and effective. The authors analyze the token ring and other network topologies and discuss the methodologies of fault tolerance and protocol integration schemes. A model token ring network has been implemented at Florida International University's Computer Engineering Laboratories to validate these concepts.","PeriodicalId":334874,"journal":{"name":"Proceedings IEEE Southeastcon '95. Visualize the Future","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132847889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ARMA model order estimation using third order cumulants 基于三阶累积量的ARMA模型阶数估计

Proceedings IEEE Southeastcon '95. Visualize the Future Pub Date : 1995-03-26 DOI: 10.1109/SECON.1995.513085

A. Al-Smadi, D. Wilkes

引用次数: 4

Modernization and expansion of an existing electric power plant 对现有发电厂进行现代化改造和扩建

Proceedings IEEE Southeastcon '95. Visualize the Future Pub Date : 1995-03-26 DOI: 10.1109/SECON.1995.513055

F. J. Hernández, A. Samra

{"title":"Modernization and expansion of an existing electric power plant","authors":"F. J. Hernández, A. Samra","doi":"10.1109/SECON.1995.513055","DOIUrl":"https://doi.org/10.1109/SECON.1995.513055","url":null,"abstract":"When modernizing or expanding a power plant, a thorough review should be made of the entire system regarding present and future requirements. The focus should be on obtaining a more economical, flexible, and reliable system. In this paper, a comprehensive study to modernize and expand an existing power plant is presented. The study is based on: part of the system is relatively new and still has a long service life that doesn't need to be modernized, old and obsolete units to be replaced with new units that solves the problem of meeting the load demand and spinning reserve, higher level of voltages to be used in generation to reduce the short circuit currents and reduce expenditures on protection equipment, and new design is based on the possibility that there will be other future expansions. Computer programs are used to perform power flow studies, short circuit current calculation, system protection coordination, and stability analysis on the system before and after modifications. The results are analyzed and used to recommend a more economical, reliable, and safe system that can meet the load demand, provides the needed spinning reserve of the plant, and give the provision of future load increases.","PeriodicalId":334874,"journal":{"name":"Proceedings IEEE Southeastcon '95. Visualize the Future","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122482428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Self partitioning backpropagation network for target recognition 目标识别的自划分反向传播网络

Proceedings IEEE Southeastcon '95. Visualize the Future Pub Date : 1995-03-26 DOI: 10.1109/SECON.1995.513052

H. Ranganath, D. Kerstetter

{"title":"Self partitioning backpropagation network for target recognition","authors":"H. Ranganath, D. Kerstetter","doi":"10.1109/SECON.1995.513052","DOIUrl":"https://doi.org/10.1109/SECON.1995.513052","url":null,"abstract":"A method for qualifying the degree of noncooperation that exists among the target members of the training set is presented. Both the network architecture and the training algorithm are taken into consideration while computing non-cooperation measures. Based on these measures, the network automatically creates several topologically identical partitions. Each partition learns a subset of the targets. The partitioning takes place only when necessary and requires minima computation. Each partition is simple with only one hidden layer and one node in the output layer. A fusion network combines partial results to produce the final response. Simulation results indicate that the method is robust and capable of self organization to overcome the ill effects of non-cooperating targets in the training set. Thus the network complexity and training time are significantly reduced. The self partitioning neural network (SPNN) approach has been tested through extensive simulation using more than 15 sets of real ATR data provided by the US Army Missile Command. Each data set consisted of hundreds of images which were extracted by the target detection system from the sensor's field of view for further processing. The study has indicated that the SPNN approach has the potential for use in real-time target recognition applications.","PeriodicalId":334874,"journal":{"name":"Proceedings IEEE Southeastcon '95. Visualize the Future","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120962925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Using genetic algorithms to solve Boolean equations 利用遗传算法求解布尔方程

Proceedings IEEE Southeastcon '95. Visualize the Future Pub Date : 1995-03-26 DOI: 10.1109/SECON.1995.513114

J. Tucker, S.K. Stover

引用次数: 1

A novel approach to design a massively parallel application specific architecture for image recognition systems 为图像识别系统设计大规模并行应用特定架构的新方法

Proceedings IEEE Southeastcon '95. Visualize the Future Pub Date : 1995-03-26 DOI: 10.1109/SECON.1995.513105

B. S. Farroha, R. G. Deshmukh

{"title":"A novel approach to design a massively parallel application specific architecture for image recognition systems","authors":"B. S. Farroha, R. G. Deshmukh","doi":"10.1109/SECON.1995.513105","DOIUrl":"https://doi.org/10.1109/SECON.1995.513105","url":null,"abstract":"The goal of the paper is to present a novel approach for designing massively parallel architectures for image recognition systems. Massive parallel hardware produces high speed image recognition. Hardware architectures work much faster and are more effective for application specific processing than a software-based image recognition system. The concept of designing optimal image recognition systems with high speed, low complexity, good portability, and low cost has been present for a long time. The authors have considered the basic design factors, simple and regular design, concurrency and communication, and balancing computation with I/O. The technique presented provides a new method of designing an image recognition system by concentrating on modularity and massive parallelism. This is accomplished through the design of a processing element layer, local communicator layer, and network of new image layer. The processing element (PE) layer performs the basic recognition functions on individual pixels through logical operations. Both the local communicator and network of new image layers institute a mesh network topology, which has proven to be the fastest and most efficient. The local communicator layer has the most important function, it communicates with the other two layers, combines results from the PE layer, and houses the main control unit. All layers work simultaneously, or in other words, in a parallel fashion. The flow diagram of a CAD designer algorithm, based on this new design technique, is presented.","PeriodicalId":334874,"journal":{"name":"Proceedings IEEE Southeastcon '95. Visualize the Future","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128147624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A comparison of SPOX and C implementations of a LPC vocoder on the TMS320C30 EVM LPC声码器在TMS320C30 EVM上的SPOX和C实现比较

Proceedings IEEE Southeastcon '95. Visualize the Future Pub Date : 1995-03-26 DOI: 10.1109/SECON.1995.513095

D. Kilpatrick, T. Jannett

引用次数: 0

HyperPascal-an architecture independent Pascal interface for parallel programming 一个架构独立的Pascal接口，用于并行编程

Proceedings IEEE Southeastcon '95. Visualize the Future Pub Date : 1995-03-26 DOI: 10.1109/SECON.1995.513061

S. Bhandarkar, B. Edwards

引用次数: 2

Integrating the portable APPN protocol stack into a multiprotocol router 将便携式APPN协议栈集成到多协议路由器中

Proceedings IEEE Southeastcon '95. Visualize the Future Pub Date : 1995-03-26 DOI: 10.1109/SECON.1995.513072

C. Alexander, C. A. Carriker

{"title":"Integrating the portable APPN protocol stack into a multiprotocol router","authors":"C. Alexander, C. A. Carriker","doi":"10.1109/SECON.1995.513072","DOIUrl":"https://doi.org/10.1109/SECON.1995.513072","url":null,"abstract":"Advanced Peer-to-Peer Networking (APPN), including High Performance Routing (HPR) and Dependent LU Requester (DLUR), has been implemented as a portable code base. This paper provides an overview of APPN functionality, and then examines the five interfaces that must be met to integrate the portable APPN code into a multiprotocol router: operating system, configuration, data link control (DLC), HPR's network control layer (NCL), and network management. Operating system portability is achieved through a system services interface layer. Node configuration is managed by a layer that interfaces between platform-specific configuration mechanisms and a verb-based API at the top of the portable stack. The DLC and NCL interfaces are supported by lagers at the bottom of the portable APPN stack; the DLC layer provides a common interface to system-dependent data link control implementations for intermediate session routing, while NCL serves a similar purpose, encompassing priority-based forwarding, for High Performance Routing. Network management interfaces are available for SNA management services and SNMP. Each of interfaces to the portable APPN protocol stack and the associated design issues are described in the context of a multiprotocol router implementation.","PeriodicalId":334874,"journal":{"name":"Proceedings IEEE Southeastcon '95. Visualize the Future","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134086414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and performance analysis of a 32/spl times/32 hybrid ATM switch architecture 一种32/spl times/32混合ATM交换机架构的设计与性能分析

Proceedings IEEE Southeastcon '95. Visualize the Future Pub Date : 1995-03-26 DOI: 10.1109/SECON.1995.513050

S. Kumar, H. Sendaula

{"title":"Design and performance analysis of a 32/spl times/32 hybrid ATM switch architecture","authors":"S. Kumar, H. Sendaula","doi":"10.1109/SECON.1995.513050","DOIUrl":"https://doi.org/10.1109/SECON.1995.513050","url":null,"abstract":"Services offered within fibre-based asynchronous transfer mode (ATM) networks may range from circuit emulations, where extremely low cell loss rates are essential, to high-speed variable rate services where a degree of cell loss can be tolerated but whose bandwidth requirements may be extremely bursty and unpredictable. ATM switches deployed within these networks must be extremely robust to support such a broad spectrum of high speed services and must also be scalable to elegantly incorporate future applications without any performance degradation. The authors present a high performance self routing tree/banyan/knockout based 32/spl times/32 hybrid ATM switch that can support a wide range of services having diverse performance objectives and traffic characteristics. The proposed architecture achieves high performance by utilizing a 3 stage expansion network which is completely non-blocking. The philosophy behind this design is the knockout principle which has been shown to achieve cell loss probabilities of the order of 10/sup -6/ with 8 buffers for each output regardless of the traffic load and the switch size. The expansion network is followed by a 2 stage banyan network which makes the switch partially blocking. The final stage is a fast output interface which is the only section of the switch which has to work at 8 times the link speed. The rest of the switch functions at link speed. The proposed switch, thus naturally lends itself to output queueing without any internal speedup.","PeriodicalId":334874,"journal":{"name":"Proceedings IEEE Southeastcon '95. Visualize the Future","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129878622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0