一种32/spl times/32混合ATM交换机架构的设计与性能分析

S. Kumar, H. Sendaula
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引用次数: 0

摘要

在基于光纤的异步传输模式(ATM)网络中提供的服务范围可能从电路模拟(其中极低的小区损失率是必不可少的)到高速可变速率服务(其中一定程度的小区损失率是可以容忍的,但其带宽需求可能非常突发和不可预测)。部署在这些网络中的ATM交换机必须非常健壮,以支持如此广泛的高速服务,还必须具有可扩展性,以便在不降低任何性能的情况下优雅地合并未来的应用程序。作者提出了一种高性能的基于自路由树/榕树/击倒的32/spl times/32混合ATM交换机,它可以支持具有不同性能目标和流量特征的广泛业务。所提出的架构通过利用完全无阻塞的3级扩展网络实现高性能。这种设计背后的理念是淘汰原则,该原则已被证明可以实现10/sup -6/的单元损失概率,并且无论流量负载和交换机大小如何,每个输出都有8个缓冲区。扩展网络之后是一个2级榕树网络,使交换机部分阻塞。最后阶段是一个快速输出接口,这是开关的唯一部分,它必须以8倍的链接速度工作。交换机的其余部分以链路速度工作。因此,建议的开关自然适合于输出队列,而不需要任何内部加速。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design and performance analysis of a 32/spl times/32 hybrid ATM switch architecture
Services offered within fibre-based asynchronous transfer mode (ATM) networks may range from circuit emulations, where extremely low cell loss rates are essential, to high-speed variable rate services where a degree of cell loss can be tolerated but whose bandwidth requirements may be extremely bursty and unpredictable. ATM switches deployed within these networks must be extremely robust to support such a broad spectrum of high speed services and must also be scalable to elegantly incorporate future applications without any performance degradation. The authors present a high performance self routing tree/banyan/knockout based 32/spl times/32 hybrid ATM switch that can support a wide range of services having diverse performance objectives and traffic characteristics. The proposed architecture achieves high performance by utilizing a 3 stage expansion network which is completely non-blocking. The philosophy behind this design is the knockout principle which has been shown to achieve cell loss probabilities of the order of 10/sup -6/ with 8 buffers for each output regardless of the traffic load and the switch size. The expansion network is followed by a 2 stage banyan network which makes the switch partially blocking. The final stage is a fast output interface which is the only section of the switch which has to work at 8 times the link speed. The rest of the switch functions at link speed. The proposed switch, thus naturally lends itself to output queueing without any internal speedup.
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