{"title":"一种32/spl times/32混合ATM交换机架构的设计与性能分析","authors":"S. Kumar, H. Sendaula","doi":"10.1109/SECON.1995.513050","DOIUrl":null,"url":null,"abstract":"Services offered within fibre-based asynchronous transfer mode (ATM) networks may range from circuit emulations, where extremely low cell loss rates are essential, to high-speed variable rate services where a degree of cell loss can be tolerated but whose bandwidth requirements may be extremely bursty and unpredictable. ATM switches deployed within these networks must be extremely robust to support such a broad spectrum of high speed services and must also be scalable to elegantly incorporate future applications without any performance degradation. The authors present a high performance self routing tree/banyan/knockout based 32/spl times/32 hybrid ATM switch that can support a wide range of services having diverse performance objectives and traffic characteristics. The proposed architecture achieves high performance by utilizing a 3 stage expansion network which is completely non-blocking. The philosophy behind this design is the knockout principle which has been shown to achieve cell loss probabilities of the order of 10/sup -6/ with 8 buffers for each output regardless of the traffic load and the switch size. The expansion network is followed by a 2 stage banyan network which makes the switch partially blocking. The final stage is a fast output interface which is the only section of the switch which has to work at 8 times the link speed. The rest of the switch functions at link speed. The proposed switch, thus naturally lends itself to output queueing without any internal speedup.","PeriodicalId":334874,"journal":{"name":"Proceedings IEEE Southeastcon '95. Visualize the Future","volume":"91 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design and performance analysis of a 32/spl times/32 hybrid ATM switch architecture\",\"authors\":\"S. Kumar, H. Sendaula\",\"doi\":\"10.1109/SECON.1995.513050\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Services offered within fibre-based asynchronous transfer mode (ATM) networks may range from circuit emulations, where extremely low cell loss rates are essential, to high-speed variable rate services where a degree of cell loss can be tolerated but whose bandwidth requirements may be extremely bursty and unpredictable. ATM switches deployed within these networks must be extremely robust to support such a broad spectrum of high speed services and must also be scalable to elegantly incorporate future applications without any performance degradation. The authors present a high performance self routing tree/banyan/knockout based 32/spl times/32 hybrid ATM switch that can support a wide range of services having diverse performance objectives and traffic characteristics. The proposed architecture achieves high performance by utilizing a 3 stage expansion network which is completely non-blocking. The philosophy behind this design is the knockout principle which has been shown to achieve cell loss probabilities of the order of 10/sup -6/ with 8 buffers for each output regardless of the traffic load and the switch size. The expansion network is followed by a 2 stage banyan network which makes the switch partially blocking. The final stage is a fast output interface which is the only section of the switch which has to work at 8 times the link speed. The rest of the switch functions at link speed. The proposed switch, thus naturally lends itself to output queueing without any internal speedup.\",\"PeriodicalId\":334874,\"journal\":{\"name\":\"Proceedings IEEE Southeastcon '95. Visualize the Future\",\"volume\":\"91 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-03-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings IEEE Southeastcon '95. Visualize the Future\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SECON.1995.513050\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE Southeastcon '95. Visualize the Future","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SECON.1995.513050","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and performance analysis of a 32/spl times/32 hybrid ATM switch architecture
Services offered within fibre-based asynchronous transfer mode (ATM) networks may range from circuit emulations, where extremely low cell loss rates are essential, to high-speed variable rate services where a degree of cell loss can be tolerated but whose bandwidth requirements may be extremely bursty and unpredictable. ATM switches deployed within these networks must be extremely robust to support such a broad spectrum of high speed services and must also be scalable to elegantly incorporate future applications without any performance degradation. The authors present a high performance self routing tree/banyan/knockout based 32/spl times/32 hybrid ATM switch that can support a wide range of services having diverse performance objectives and traffic characteristics. The proposed architecture achieves high performance by utilizing a 3 stage expansion network which is completely non-blocking. The philosophy behind this design is the knockout principle which has been shown to achieve cell loss probabilities of the order of 10/sup -6/ with 8 buffers for each output regardless of the traffic load and the switch size. The expansion network is followed by a 2 stage banyan network which makes the switch partially blocking. The final stage is a fast output interface which is the only section of the switch which has to work at 8 times the link speed. The rest of the switch functions at link speed. The proposed switch, thus naturally lends itself to output queueing without any internal speedup.