2014 12th IEEE International Conference on Embedded and Ubiquitous Computing最新文献_第5页

Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis 利用LegUp高级综合实现处理器/加速器嵌入式系统的自动化设计

2014 12th IEEE International Conference on Embedded and Ubiquitous Computing Pub Date : 2014-08-26 DOI: 10.1109/EUC.2014.26

B. Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S. Czajkowski, S. Brown, J. Anderson

{"title":"Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis","authors":"B. Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S. Czajkowski, S. Brown, J. Anderson","doi":"10.1109/EUC.2014.26","DOIUrl":"https://doi.org/10.1109/EUC.2014.26","url":null,"abstract":"LegUp [1] is an open-source high-level synthesis (HLS) tool that accepts a C program as input and automatically synthesizes it into a hybrid system. The hybrid system comprises an embedded processor and custom accelerators that realize user-designated compute-intensive parts of the program with improved throughput and energy efficiency. In this paper, we overview the LegUp framework and describe several recent developments: 1) support for an embedded ARM processor, as is available on Altera's recently released SoC FPGA, 2) HLS support for software parallelization schemes -- pthreads and OpenMP, 3) enhancements to LegUp's core HLS algorithms that raise the quality of the auto-generated hardware, and, 4) a preliminary debugging and verification framework providing C source-level debugging of HLS hardware. Since its first release in 2011, LegUp has been downloaded over 1000 times by groups around the world, providing a powerful platform for new research in high-level synthesis algorithms and embedded systems design.","PeriodicalId":331736,"journal":{"name":"2014 12th IEEE International Conference on Embedded and Ubiquitous Computing","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121419047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

Instruction Cache in Hard Real-Time Systems: Modeling and Integration in Scheduling Analysis Tools with AADL 硬实时系统中的指令缓存:基于AADL的调度分析工具的建模与集成

2014 12th IEEE International Conference on Embedded and Ubiquitous Computing Pub Date : 2014-08-26 DOI: 10.1109/EUC.2014.24

H. Tran, Frank Singhoff, S. Rubini, Jalil Boukhobza

{"title":"Instruction Cache in Hard Real-Time Systems: Modeling and Integration in Scheduling Analysis Tools with AADL","authors":"H. Tran, Frank Singhoff, S. Rubini, Jalil Boukhobza","doi":"10.1109/EUC.2014.24","DOIUrl":"https://doi.org/10.1109/EUC.2014.24","url":null,"abstract":"Cache prediction for real-time systems in a preemptive scheduling context is still an open issue despite its practical importance. In this paper, we propose a modeling approach for taking into account the cache memory in realtime scheduling analysis. The goal is to have a simple but practical implementation to handle the cache memory with a real-time scheduling analyzer. The proposed contribution consists of three main parts: (1) modeling the targeted system with the Architecture Analysis and Design Language (AADL), (2) applying the cache analysis methods in a real time scheduling analysis tool and (3) performing scheduling simulation to access schedulability. For such a purpose, we present an extension of both the scheduling analysis tool Cheddar and of the AADL modeling language in order to integrate the cache modeling and analysis methodology we proposed. Experiments are presented to illustrate our propositions. They provide results on analysis that show examples of the timing impact of task preemption as well as the increase in overall responses time of the task set. This impact is important and the developed tool provides means to precisely assess it.","PeriodicalId":331736,"journal":{"name":"2014 12th IEEE International Conference on Embedded and Ubiquitous Computing","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124797859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Improving the Recognition Performance of NIALM Algorithms through Technical Labeling 通过技术标注提高NIALM算法的识别性能

2014 12th IEEE International Conference on Embedded and Ubiquitous Computing Pub Date : 2014-08-26 DOI: 10.1109/EUC.2014.41

Marcel Mathis, Andreas Rumsch, R. Kistler, A. Andrushevich, A. Klapproth

引用次数: 10

Improving Energy Efficiency with Dynamic Compiler-Directed Function Unit Power Control 利用动态编译器定向功能单元功率控制提高能源效率

2014 12th IEEE International Conference on Embedded and Ubiquitous Computing Pub Date : 2014-08-26 DOI: 10.1109/EUC.2014.56

Yu Sun, Wei Zhang

引用次数: 0

CoreVA: A Configurable Resource-Efficient VLIW Processor Architecture CoreVA:一种可配置的资源高效VLIW处理器架构

2014 12th IEEE International Conference on Embedded and Ubiquitous Computing Pub Date : 2014-08-26 DOI: 10.1109/EUC.2014.11

Boris Hübener, Gregor Sievers, T. Jungeblut, Mario Porrmann, U. Rückert

{"title":"CoreVA: A Configurable Resource-Efficient VLIW Processor Architecture","authors":"Boris Hübener, Gregor Sievers, T. Jungeblut, Mario Porrmann, U. Rückert","doi":"10.1109/EUC.2014.11","DOIUrl":"https://doi.org/10.1109/EUC.2014.11","url":null,"abstract":"Mobile signal processing applications have a limited energy budget and require resource-efficient processing elements. General purpose VLIW CPUs offer a high energy efficiency and allow for the execution of a wide range of applications in this domain. In this work we present the configurable 32 bit VLIW processor architecture CoreVA. Besides the number of issue slots, it allows for a fine-grained configuration of the amount and characteristics of the processor's functional units (e.g., ALUs, MACs, or LD/ST units). A design-space exploration is performed to evaluate how these functional units impact area and power consumption. The basic configuration with one ALU, MAC, DIV, and LD/ST unit has a power consumption of 11.796 mW and an area of 0.142 mm2 at a clock frequency of 750 MHz in a 28 nm FD-SOI process. The maximum clock frequency in this process node is 833 MHz. To bear a relation of the hardware requirements to possible performance gains of the application, a signal processing algorithm is used as a benchmark to evaluate the energy consumption of different hardware configurations. The lowest energy consumption is observed with a configuration of 4 issue slots using 4 ALUs, 4 MACs, and 2 LD/ST units. This is an improvement by a factor of 1.68 compared to the single issue slot configuration.","PeriodicalId":331736,"journal":{"name":"2014 12th IEEE International Conference on Embedded and Ubiquitous Computing","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132012870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Fault-Tolerant Scheduling of Mixed-Critical Applications on Multi-processor Platforms 多处理器平台上混合关键应用的容错调度

2014 12th IEEE International Conference on Embedded and Ubiquitous Computing Pub Date : 2014-08-26 DOI: 10.1109/EUC.2014.13

M. Bagheri, G. Jervan

{"title":"Fault-Tolerant Scheduling of Mixed-Critical Applications on Multi-processor Platforms","authors":"M. Bagheri, G. Jervan","doi":"10.1109/EUC.2014.13","DOIUrl":"https://doi.org/10.1109/EUC.2014.13","url":null,"abstract":"There is a lack of mixed-criticality support in system-level design frameworks for dependable Network-on-Chip (NoC) -based multiprocessor systems. Such frameworks should address mixed-criticality in both computation and NoC communication. In Mixed-Critical (MC) systems, only the Safety-Critical (SC) parts have strict predictability and dependability requirements, but conventional methods design the whole system with pessimistic settings to ensure these requirements are satisfied. This however, results in under-utilization of computation and network resources, and a decrease in performance. In this work, we integrate support of MC applications into an existing system-level design framework of dependable NoC-based multiprocessors. This framework handles failures in both computation and inter-task communication. We address the under-utilization problem by proposing a mixed-critical scheduling method such that the overall system performance is increased but all deadlines of SC tasks are met even in the presence of transient faults. Our approach handles mixed-criticality not only in tasks but also in inter-task messages. Our experiments demonstrate performance improvement in different run-time execution environments and with different MC benchmark applications including a realistic robot control system. Performance improvement is achieved regardless of task graph size, NoC size or temporal redundancy level.","PeriodicalId":331736,"journal":{"name":"2014 12th IEEE International Conference on Embedded and Ubiquitous Computing","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129223506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A Platform for Integrating Physical Devices in the Internet of Things 物联网物理设备集成平台

2014 12th IEEE International Conference on Embedded and Ubiquitous Computing Pub Date : 2014-08-01 DOI: 10.1109/EUC.2014.42

Paulo F. Pires, Everton Cavalcante, T. Barros, Flávia Coimbra Delicato, T. Batista, Bruno Costa

{"title":"A Platform for Integrating Physical Devices in the Internet of Things","authors":"Paulo F. Pires, Everton Cavalcante, T. Barros, Flávia Coimbra Delicato, T. Batista, Bruno Costa","doi":"10.1109/EUC.2014.42","DOIUrl":"https://doi.org/10.1109/EUC.2014.42","url":null,"abstract":"The Internet of Things (IoT) has emerged as a paradigm in which smart things actively collaborate among them and with other physical and virtual objects available in the Web in order to perform high-level tasks. IoT environments are typically characterized by a high degree of heterogeneity, thus encompassing devices with different capabilities, functionalities, and network protocols. In such a scenario, it is necessary to provide abstractions for physical devices and services to applications and end-users, as well as means to manage the interoperability between such heterogeneous elements. In this context, we introduce EcoDiF (Web Ecosystem of Physical Devices), a Web-based platform for integrating heterogeneous physical devices with applications and users in order to provide services to support real-time data control, visualization, processing, and storage. In this paper, we present the main features of EcoDiF and detail its architecture and implementation, which is based on well-known Web technologies such as HTTP, REST, EEML, and EMML. Furthermore, we present a preliminary evaluation of an EcoDiF prototype through proof-of-concept applications from different domains as well as a performance analysis of the platform.","PeriodicalId":331736,"journal":{"name":"2014 12th IEEE International Conference on Embedded and Ubiquitous Computing","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121930182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 37

Hop-Based Priority Scheduling to Improve Worst-Case Inter-core Communication Latency 改进最坏情况下核间通信延迟的hop优先级调度

2014 12th IEEE International Conference on Embedded and Ubiquitous Computing Pub Date : 2014-08-01 DOI: 10.1109/EUC.2014.17

Yiqiang Ding, Wei Zhang

引用次数: 1