Hop-Based Priority Scheduling to Improve Worst-Case Inter-core Communication Latency

Abstract

In this paper, we first propose a static analysis approach to estimate the maximum value of the worst-case latency of all possible communications in a Chip Multi-Processor (CMP) with a 2D-Mesh Network-on-Chip (NoC), which is called the Worst-case Inter-core Communication Latency (WICL). Then the Hop-based Priority scheduling approach is proposed for a 2D-Mesh NoC to improve its WICL. Our experimental results indicate that the Hop-based Priority (HP) scheduling can reduce the WICL by 50% in average for various network sizes compared with that of the FIFO scheduling.