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A NFA-based programmable regular expression match engine 一个基于nba的可编程正则表达式匹配引擎
Symposium on Architectures for Networking and Communications Systems Pub Date : 2009-10-19 DOI: 10.1145/1882486.1882499
D. Pao
{"title":"A NFA-based programmable regular expression match engine","authors":"D. Pao","doi":"10.1145/1882486.1882499","DOIUrl":"https://doi.org/10.1145/1882486.1882499","url":null,"abstract":"In this poster, we present a programmable hardware architecture to speed up the matching of regular expressions. The match engine is modeled as non-deterministic finite automata (NFA) with auxiliary hardware features to process repetition of sub-patterns without unrolling. The computation is table-driven and the system throughput is deterministic. The lookup tables are implemented using ternary content addressable memory (TCAM). The overall table size is approximately equal to the number of transition edges in the NFA. Incremental changes to the pattern set can be accommodated by modifying the contents of the lookup tables without reconfiguring the hardware.","PeriodicalId":329300,"journal":{"name":"Symposium on Architectures for Networking and Communications Systems","volume":"380 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115925611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A path combinational method for multiple pattern matching 多模式匹配的路径组合方法
Symposium on Architectures for Networking and Communications Systems Pub Date : 2009-10-19 DOI: 10.1145/1882486.1882507
Tian Song, Dongsheng Wang
{"title":"A path combinational method for multiple pattern matching","authors":"Tian Song, Dongsheng Wang","doi":"10.1145/1882486.1882507","DOIUrl":"https://doi.org/10.1145/1882486.1882507","url":null,"abstract":"Multiple pattern matching architecture is critical for content inspection based network security applications, especially for high speed network or large pattern sets. This paper presents a method to optimize the potential memory usage for multiple string or regular expression matching by the idea of combining DFA's paths, named isomorphic path combination (IMPC). To achieve IMPC, a novel multiple pattern matching algorithm is proposed, which is based on Cached DFA (CDFA). Compared to extended AC algorithm based on DFA, our method on CDFA can reduce 78.6% states for Snort pattern set, which results in one of the most memory efficient methods. More important is that our method can be embedded to other algorithms as the optimization.","PeriodicalId":329300,"journal":{"name":"Symposium on Architectures for Networking and Communications Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117237418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High throughput architecture for packet classification using FPGA 基于FPGA的数据包分类高吞吐量架构
Symposium on Architectures for Networking and Communications Systems Pub Date : 2009-10-19 DOI: 10.1145/1882486.1882500
Zhang Tao, Yonggang Wang, Lijun Zhang, Yang Yang
{"title":"High throughput architecture for packet classification using FPGA","authors":"Zhang Tao, Yonggang Wang, Lijun Zhang, Yang Yang","doi":"10.1145/1882486.1882500","DOIUrl":"https://doi.org/10.1145/1882486.1882500","url":null,"abstract":"To avoid packet classification from being the performance bottleneck in network devices, one-chip solution hardware packet classifier based on HiCuts algorithm is designed and implemented in single chip of FPGA. The compact data structure and the optimized combination of memory organization with high degree parallel and pipeline architecture make the classifier running at very high speed. The simulation and implementation tests show our design reaches OC-768 throughput even for a large rule set with 26K rules while only consuming limited logic resource of the FPGA. This low cost one-chip hardware solution can effectively off-load data processing burden from the CPU of data path in network devices.","PeriodicalId":329300,"journal":{"name":"Symposium on Architectures for Networking and Communications Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122586637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
EINIC: an architecture for high bandwidth network I/O on multi-core processors EINIC:多核处理器上的高带宽网络I/O架构
Symposium on Architectures for Networking and Communications Systems Pub Date : 2009-10-19 DOI: 10.1145/1882486.1882503
Guangdeng Liao, L. Bhuyan, Danhua Guo, Steve R. King
{"title":"EINIC: an architecture for high bandwidth network I/O on multi-core processors","authors":"Guangdeng Liao, L. Bhuyan, Danhua Guo, Steve R. King","doi":"10.1145/1882486.1882503","DOIUrl":"https://doi.org/10.1145/1882486.1882503","url":null,"abstract":"This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacity. Similar to prior work, EINIC integrates a redesigned NIC onto a CPU. However, we extend the integrated NIC (INIC) to multicore platforms and examine its behaviors with the network receiving optimization. Additionally, by exploiting NICs proximity to CPUs, we also design an I/O-aware last level shared cache (LLC). Our I/O-aware design allows us to split the cache into an I/O cache and a general cache in a flexible way. It ameliorates cache interferences between network and non-network data. Our simulation results show that EINIC not only attacks the mismatch, but also ameliorates the cache interference.","PeriodicalId":329300,"journal":{"name":"Symposium on Architectures for Networking and Communications Systems","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125643893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Theoretic analysis of finite automata for memory-based pattern matching 基于记忆的模式匹配有限自动机的理论分析
Symposium on Architectures for Networking and Communications Systems Pub Date : 2009-10-19 DOI: 10.1145/1882486.1882510
L. Vespa, N. Weng
{"title":"Theoretic analysis of finite automata for memory-based pattern matching","authors":"L. Vespa, N. Weng","doi":"10.1145/1882486.1882510","DOIUrl":"https://doi.org/10.1145/1882486.1882510","url":null,"abstract":"In the midst of vastly numbered and quickly growing internet security threats, Network Intrusion Detection System (NIDS) [2] becomes more important to network security every day. Vital to effective NIDS is a multi-pattern matching engine which requires deterministic performance and adaptability to new threats [3]. Memory-based Deterministic Finite Automata (DFA) are ideal for pattern matching but have severe memory requirements [1] that make them difficult to implement. Many previous heuristic techniques have been proposed to reduce memory requirements, however in this paper, we aim to effectively understand the basic relationship between DFA characteristics and memory, in order to create minimal memory DFA implementations. We show what DFA characteristics either cause or reduce memory requirements, as well as how to optimize DFA to exploit those characteristics. Specifically, we introduce the concepts of State Independence and State Irregularity, which are DFA characteristics that can reduce memory waste and allow for memory reuse. Furthermore, we introduce DFA normalization which optimizes DFA to fully exploit these characteristics. Altogether this work serves as a source for how to extract and utilize DFA characteristics to create minimal memory implementations.","PeriodicalId":329300,"journal":{"name":"Symposium on Architectures for Networking and Communications Systems","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132040881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
OASis: towards extensible open-architecture services platforms OASis:面向可扩展的开放体系结构服务平台
Symposium on Architectures for Networking and Communications Systems Pub Date : 2009-10-19 DOI: 10.1145/1882486.1882502
Yaxuan Qi, Fei He, Xiang Wang, Xinming Chen, Y. Xue, Jun Li
{"title":"OASis: towards extensible open-architecture services platforms","authors":"Yaxuan Qi, Fei He, Xiang Wang, Xinming Chen, Y. Xue, Jun Li","doi":"10.1145/1882486.1882502","DOIUrl":"https://doi.org/10.1145/1882486.1882502","url":null,"abstract":"In this paper, we propose an extensible Open-Architecture Services platform (OASis) for high-performance network processing. OASis embraces recent advances of open technologies, including open source software, open system standards and open network architectures. Three programming models are proposed for target-specific processing modules: a multi-granularity packet processing model for network processing; a thread-isolated parallel programming model for service processing; and a message-based management model for centralized system administration. As an application example of OASis, a Unified Threat Management (UTM) prototype is implemented. This prototype provides multiple network security services, including stateful firewall, intrusion detection, and virus scanning. Experimental results show that, the OASis-UTM prototype can achieve 40Gbps stateful firewall performance together with 4--8Gbps intrusion detection and anti-virus performance on a 12U 14-slot ATCA platform.","PeriodicalId":329300,"journal":{"name":"Symposium on Architectures for Networking and Communications Systems","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123026550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Testbed for evaluating worm containment systems 评估蠕虫防护系统的试验台
Symposium on Architectures for Networking and Communications Systems Pub Date : 2009-10-19 DOI: 10.1145/1882486.1882529
R. Chakrovorty, L. Vespa, N. Weng
{"title":"Testbed for evaluating worm containment systems","authors":"R. Chakrovorty, L. Vespa, N. Weng","doi":"10.1145/1882486.1882529","DOIUrl":"https://doi.org/10.1145/1882486.1882529","url":null,"abstract":"Dangerous worms like CodeRed or Slammer can spread millions of probe packets in just seconds which can result in thousands of infected hosts and large losses. Fast and effective containment strategies are crucially important to protect the Internet Infrastructure. Toward this goal of fast and effective worm containment, different techniques have been presented such as address blacklisting and content filtering [3], anomaly detection [6] and signature-based detection [5]. Meanwhile recently developed worm models [1] enable us to develop a testbed to accurately and quickly evaluate the efficiency of these defense mechanisms. In this paper, we present a testbed which utilizes software agents to allow large scale simulation with individual host functionality. We utilize this testbed to evaluate our containment systems in terms of security and performance tradeoff.","PeriodicalId":329300,"journal":{"name":"Symposium on Architectures for Networking and Communications Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131604668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A block-based reservation architecture for the implementation of large packet buffers 用于实现大数据包缓冲区的基于块的保留体系结构
Symposium on Architectures for Networking and Communications Systems Pub Date : 2009-10-19 DOI: 10.1145/1882486.1882501
Hao Wang, Bill Lin
{"title":"A block-based reservation architecture for the implementation of large packet buffers","authors":"Hao Wang, Bill Lin","doi":"10.1145/1882486.1882501","DOIUrl":"https://doi.org/10.1145/1882486.1882501","url":null,"abstract":"DRAM is typically needed to implement large packet buffers, but DRAM devices have worst-case random access latencies that are too slow to match the bandwidth requirements of high-performance routers. Existing DRAM-based architectures for supporting linespeed queue operations can be classified into three categories: prefetching-based [1], randomization-based [2], and reservation-based [3]. They are all based on interleaving memory accesses across multiple parallel DRAM banks for achieving higher memory bandwidths, but they differ in their packet placement and memory operation scheduling mechanisms. Each class of architectures has its own benefits. For router architectures where the departure times of packets can be deterministically calculated before the packets are inserted into the packet buffer, the reservation-based approach has the nice property that in-time packet retrievals can be guaranteed. Reservation-based architectures work by constructive placement of packets and scheduling of memory operations based on the departure times of packets.","PeriodicalId":329300,"journal":{"name":"Symposium on Architectures for Networking and Communications Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132590459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Experience with high-speed automated application-identification for network-management 具有网络管理中高速自动化应用识别的经验
Symposium on Architectures for Networking and Communications Systems Pub Date : 2009-10-19 DOI: 10.1145/1882486.1882539
M. Canini, Wei Li, M. Zádník, A. Moore
{"title":"Experience with high-speed automated application-identification for network-management","authors":"M. Canini, Wei Li, M. Zádník, A. Moore","doi":"10.1145/1882486.1882539","DOIUrl":"https://doi.org/10.1145/1882486.1882539","url":null,"abstract":"AtoZ, an automatic traffic organizer, provides control of how network-resources are used by applications. It does this by combining the high-speed packet processing of the NetFPGA with an efficient method for application-behavior labeling. AtoZ can control network resources by prohibiting certain applications and controlling the resources available to others. We discuss deployment experience and use real traffic to illustrate how such an architecture enables several distinct features: high accuracy, high throughput, minimal delay, and efficient packet labeling --- all in a low-cost, robust configuration that works alongside the enterprise access-router.","PeriodicalId":329300,"journal":{"name":"Symposium on Architectures for Networking and Communications Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116912883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
A novel 3D layer-multiplexed on-chip network 一种新颖的三维层复用片上网络
Symposium on Architectures for Networking and Communications Systems Pub Date : 2009-10-19 DOI: 10.1145/1882486.1882517
R. Ramanujam, Bill Lin
{"title":"A novel 3D layer-multiplexed on-chip network","authors":"R. Ramanujam, Bill Lin","doi":"10.1145/1882486.1882517","DOIUrl":"https://doi.org/10.1145/1882486.1882517","url":null,"abstract":"Recently, a near-optimal oblivious routing algorithm for 3D mesh networks called Randomized Partially-Minimal (RPM) routing was proposed [12], which works by load-balancing traffic across vertical layers and routing minimally on each horizontal layer. It achieves optimal worst-case throughput when the network radix k is even and within a factor of 1/k2 of optimal when k is odd, and it achieves significantly lower latencies than Valiant routing [18], the best previously known optimal worst-case throughput algorithm. This paper presents a novel layer-multiplexed (LM) architecture for 3D on-chip networks that exploits the optimality of RPM together with the short inter-layer wiring delays enabled in 3D technology. The LM architecture replaces the one-layer-per-hop routing in a 3D mesh with simpler vertical demultiplexing and multiplexing structures. The proposed LM architecture can achieve the same worst-case throughput as a 3D mesh by adapting RPM routing to the LM architecture. However, the LM architecture consumes 27% less power, occupies 27% less area, attains 14.5% higher average throughput, and achieves 33% lower worst-case hop count for a symmetric 4x4x4 mesh topology. On an asymmetric 8 x 8 x 4 mesh, the LM architecture achieves comparable average-case throughput to a 3D mesh, but consumes 26% less power, takes up 27% less area and attains 20% lower worst-case hop count.","PeriodicalId":329300,"journal":{"name":"Symposium on Architectures for Networking and Communications Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130573065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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