High throughput architecture for packet classification using FPGA

Abstract

To avoid packet classification from being the performance bottleneck in network devices, one-chip solution hardware packet classifier based on HiCuts algorithm is designed and implemented in single chip of FPGA. The compact data structure and the optimized combination of memory organization with high degree parallel and pipeline architecture make the classifier running at very high speed. The simulation and implementation tests show our design reaches OC-768 throughput even for a large rule set with 26K rules while only consuming limited logic resource of the FPGA. This low cost one-chip hardware solution can effectively off-load data processing burden from the CPU of data path in network devices.