A block-based reservation architecture for the implementation of large packet buffers

DRAM is typically needed to implement large packet buffers, but DRAM devices have worst-case random access latencies that are too slow to match the bandwidth requirements of high-performance routers. Existing DRAM-based architectures for supporting linespeed queue operations can be classified into three categories: prefetching-based [1], randomization-based [2], and reservation-based [3]. They are all based on interleaving memory accesses across multiple parallel DRAM banks for achieving higher memory bandwidths, but they differ in their packet placement and memory operation scheduling mechanisms. Each class of architectures has its own benefits. For router architectures where the departure times of packets can be deterministically calculated before the packets are inserted into the packet buffer, the reservation-based approach has the nice property that in-time packet retrievals can be guaranteed. Reservation-based architectures work by constructive placement of packets and scheduling of memory operations based on the departure times of packets.