2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)最新文献_第4页

Lessons learned during the implementation of the BVR Wireless Sensor Network protocol on SunSPOTs 在太阳黑子上实施BVR无线传感器网络协议的经验教训

2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW) Pub Date : 2010-04-19 DOI: 10.1109/IPDPSW.2010.5470862

Ralph robert Erdt, M. Gergeleit

引用次数: 1

Particle Swarm Optimization to solve the Vehicle Routing Problem with Heterogeneous fleet, Mixed Backhauls, and time windows 粒子群算法求解异构车队、混合回程和时间窗车辆路径问题

2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW) Pub Date : 2010-04-19 DOI: 10.1109/IPDPSW.2010.5470702

Farah Belmecheri, C. Prins, F. Yalaoui, L. Amodeo

引用次数: 6

Prototype for a large-scale static timing analyzer running on an IBM Blue Gene 在IBM Blue Gene上运行的大型静态定时分析仪的原型

2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW) Pub Date : 2010-04-19 DOI: 10.1109/IPDPSW.2010.5470757

A. Holder, C. Carothers, Kerim Kalafala

{"title":"Prototype for a large-scale static timing analyzer running on an IBM Blue Gene","authors":"A. Holder, C. Carothers, Kerim Kalafala","doi":"10.1109/IPDPSW.2010.5470757","DOIUrl":"https://doi.org/10.1109/IPDPSW.2010.5470757","url":null,"abstract":"This paper focuses on parallelization of the classic static timing analysis (STA) algorithm for verifying timing characteristics of digital integrated circuits. Given ever-increasing circuit complexities, including the need to analyze circuits with billions of transistors, across potentially thousands of process corners, with accuracy tolerances down to the picosecond range, sequential execution of STA algorithms is quickly becoming a bottleneck to the overall chip design closure process. A message passing based parallel processing technique for performing STA leveraging an IBM Blue Gene/L supercomputing platform is presented. Results are collected for a small industrial 65 nm benchmarking design, where the algorithm demonstrates speedup of nearly 39 times on 64 processors and a peak of 119 times (without partitioning costs, speedup is 263 times) on 1024 processors. With an idealized synthetic circuit, the algorithm demonstrated 259 times speedup, 925 times speedup without partitioning overhead, on 1024 processors. To the best of our knowledge, this is the first result demonstrating scalable STA on the IBM Blue Gene.","PeriodicalId":329280,"journal":{"name":"2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134246880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

High precision integer multiplication with a graphics processing unit 高精度整数乘法与图形处理单元

2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW) Pub Date : 2010-04-19 DOI: 10.1109/IPDPSW.2010.5470814

Niall Emmart, C. Weems

{"title":"High precision integer multiplication with a graphics processing unit","authors":"Niall Emmart, C. Weems","doi":"10.1109/IPDPSW.2010.5470814","DOIUrl":"https://doi.org/10.1109/IPDPSW.2010.5470814","url":null,"abstract":"In this paper we evaluate the potential for using an NVIDIA graphics processing unit (GPU) to accelerate high precision integer multiplication. The reported peak vector performance for a typical GPU appears to offer considerable potential for accelerating such a regular computation. Because of limitations in the on-chip memory, the high cost of kernel launches, and the particular nature of the architecture's support for parallelism, we found it necessary to use a hybrid algorithmic approach to obtain good performance. On the GPU itself we use an adaptation of the Strassen FFT algorithm to multiply 32KB chunks, while on the CPU we adapt the Karatsuba divide-and-conquer approach to optimize the application of the GPU's partial multiplies, which are viewed as “digits” by our implementation of Karatsuba. Even with this approach, the result is at best a modest increase in performance, compared with executing the same multiplication using the GMP package on a CPU at a comparable technology node. We identify the sources of this lackluster performance and discuss the likely impact of planned advances in GPU architecture.","PeriodicalId":329280,"journal":{"name":"2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134171643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Modeling bounds on migration overhead for a traveling thread architecture 对移动线程架构的迁移开销进行建模

2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW) Pub Date : 2010-04-19 DOI: 10.1109/IPDPSW.2010.5470686

P. Fratta, P. Kogge

{"title":"Modeling bounds on migration overhead for a traveling thread architecture","authors":"P. Fratta, P. Kogge","doi":"10.1109/IPDPSW.2010.5470686","DOIUrl":"https://doi.org/10.1109/IPDPSW.2010.5470686","url":null,"abstract":"Heterogeneous multicore architectures have gained widespread use in the general purpose and scientific computing communities, and architects continue to investigate techniques for easing the burden of parallelization from the programmer. This paper presents a new class of heterogeneous multicores that leverages past work in architectures supporting the execution of traveling threads. These traveling threads execute on simple cores distributed across the chip and can move up the hierarchy and between cores based on data locality. This new design offers the benefits of improved performance at lower energy and power density than centralized counterparts through intelligent data placement and cooperative caching policies. We employ a methodology consisting of mathematical modeling and simulation to estimate the upper bounds on migration overhead for various architectural organizations. Results illustrate that the new architecture can match the performance of a conventional processor with reasonable thread sizes. We have observed that between 0.04 and 7.09 instructions per migration (IPM) (1.88 IPM on average) are sufficient to match the performance of the conventional processor. These results confirm that this distributed architecture and corresponding execution model offer promising potential in overcoming the design challenges of centralized counterparts.","PeriodicalId":329280,"journal":{"name":"2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132901599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Randomized self-stabilizing leader election in preference-based anonymous trees 基于偏好的匿名树随机自稳定领导选举

2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW) Pub Date : 2010-04-19 DOI: 10.1142/S0129054112400394

Daniel Fajardo-Delgado, José Alberto Fernández-Zepeda, A. Bourgeois

引用次数: 5

Flexible IP cores for the k-NN classification problem and their FPGA implementation 用于k-NN分类问题的柔性IP核及其FPGA实现

2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW) Pub Date : 2010-04-19 DOI: 10.1109/IPDPSW.2010.5470733

E. Manolakos, I. Stamoulias

引用次数: 13

Clairvoyant site allocation of jobs with highly variable service demands in a computational grid 计算网格中具有高度可变服务需求的作业的透视站点分配

2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW) Pub Date : 2010-04-19 DOI: 10.1109/IPDPSW.2010.5470781

S. Zikos, H. Karatza

引用次数: 7

Scalability analysis of embarassingly parallel applications on large clusters 大型集群上令人尴尬的并行应用程序的可伸缩性分析

2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW) Pub Date : 2010-04-19 DOI: 10.1109/IPDPSW.2010.5470724

Fabrício A. B. Silva, H. Senger

引用次数: 4

Parallel external sorting for CUDA-enabled GPUs with load balancing and low transfer overhead 支持cuda的gpu的并行外部排序，具有负载平衡和低传输开销

2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW) Pub Date : 2010-04-19 DOI: 10.1109/IPDPSW.2010.5470833

H. Peters, Ole Schulz-Hildebrandt, N. Luttenberger

引用次数: 17