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3D-NWA: A Nested-Winograd Accelerator for 3D CNNs 3D- nwa:用于3D cnn的嵌套winograd加速器
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9963033
Huafeng Ye, Huipeng Deng, Jian Wang, Mingyu Wang, Zhiyi Yu
{"title":"3D-NWA: A Nested-Winograd Accelerator for 3D CNNs","authors":"Huafeng Ye, Huipeng Deng, Jian Wang, Mingyu Wang, Zhiyi Yu","doi":"10.1109/ICTA56932.2022.9963033","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963033","url":null,"abstract":"3D Convolutional neural networks (3D CNNs) perform better in some scenarios, such as video understanding and 3D medical image diagnosis. With the increase in the dimension and size of the convolution kernel, CNN's computational complexity and implementation difficulty increase severely. Winograd transformation can significantly reduce the number of multiplications in convolution operations. However, large convolution filters will bring numerical instability. In this article, we presented a novel method called 3D nested Winograd algorithm to address the problem. Compared with the state-of-art OLA-Winograd algorithm, the proposed algorithm reduces the multiplications by 1.72 to 5.83× for computing 5 × 5 × 5 to 9 × 9 × 9 convolutions. Finally, we demonstrate the efficiency of 3D-NWA on the FPGA platform (Xilinx VCU118) and achieve highest DSP efficiency up to 4.67× compared with the state-of-art accelerators.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117131038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Novel Concept of using Double Threshold Voltage Coupling to Improve the linearity of AlGaN/GaN HEMTs for millimeter-wave applications 利用双阈值电压耦合提高毫米波应用中AlGaN/GaN hemt线性度的新概念
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9963079
Pengfei Wang, Minhan Mi, Sirui An, Xiang Du, Xiao-hua Ma, Yue Hao
{"title":"A Novel Concept of using Double Threshold Voltage Coupling to Improve the linearity of AlGaN/GaN HEMTs for millimeter-wave applications","authors":"Pengfei Wang, Minhan Mi, Sirui An, Xiang Du, Xiao-hua Ma, Yue Hao","doi":"10.1109/ICTA56932.2022.9963079","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963079","url":null,"abstract":"In this letter, we demonstrate an AlGaN/GaN HEMT fabricated by synthesizing recess and planar devices along the gate width and incorporating N2O plasma treatment to form an oxide layer at the gate electrode of the proposed HEMT. The transconductance curve of the fabricated device has a plateau region larger than 7 V, with a flattened response curve of fT/fmaxwith respect to the gate bias voltage. At the operating frequency of 30 GHz, the maximum power-added efficiency (PAE) is 41%, the value of the power density ($mathrm{P}_{mathrm{o}mathrm{u}mathrm{t}}$ is 5.3 W/mm, and the associated 1dB compression point $(mathrm{p}_{mathrm{l}mathrm{d}mathrm{B}^{)}}$ is 28 dBm. The device presented in this article has excellent potential for millimeter-wave applications where high linearity is essential.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126548017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A High-Density Large-Ratio Fuse Based Oxide Devices for One-time-programmable Memory Applications 用于一次性可编程存储器的高密度大比熔丝氧化物器件
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9962988
Xuecheng Cui, Dong Liu, Jifang Cao, Xiao Yu, Bing Chen
{"title":"A High-Density Large-Ratio Fuse Based Oxide Devices for One-time-programmable Memory Applications","authors":"Xuecheng Cui, Dong Liu, Jifang Cao, Xiao Yu, Bing Chen","doi":"10.1109/ICTA56932.2022.9962988","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962988","url":null,"abstract":"In this paper, the oxide fused and anti-fused behavior has been observed in a simple metal-oxide-metal device: Pt/HfO2/NiOx/Ni. The anti-fused state and fused state can be achieved by applying program voltage on the devices with or without current compliance, respectively. And the resistance window of the two states reaches about 109, which can effectively reduce the possibility of incorrect programming. It also showed excellent retention characteristics and a simple structure friendly for integration. It can be well used in the field of high reliability of one-time programmable memory.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124495987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.3 V-4 V Input Voltage Range, 0.7 V Cold Start Boost Converter with 1 V Internal Voltage Supply Generator by Using 0.18 µm CMOS Process for Energy Harvesting Application 一种0.3 V- 4v输入电压范围，0.7 V冷启动升压变换器，采用0.18µm CMOS工艺，内置1v电压电源发生器，用于能量收集应用
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9963039
Zheng Lu, Shiquan Fan, Weiqing Ma, Ying Xie, Li Geng
{"title":"A 0.3 V-4 V Input Voltage Range, 0.7 V Cold Start Boost Converter with 1 V Internal Voltage Supply Generator by Using 0.18 µm CMOS Process for Energy Harvesting Application","authors":"Zheng Lu, Shiquan Fan, Weiqing Ma, Ying Xie, Li Geng","doi":"10.1109/ICTA56932.2022.9963039","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963039","url":null,"abstract":"In this paper, a wide input range boost converter is proposed. In consideration of the wide input voltage range, especially at very low input voltage, to guarantee the internal control circuit (ring oscillator and PFM controller) can operate correctly, an internal adaptive supply voltage generator is designed to produce 1 V supply voltage. The boost converter is fabricated with standard 0.18 µm 5P0 CMOS process. The active area of the boost converter is nearly 0.5 mm2. Measured results show that the boost converter can cold start with 700 mV input voltage and operate with input voltage range of 0.3 V-4 V, which demonstrate the design concepts of boost converter well.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133945223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 20W Ka-Band Dual-Port Power Amplifier for Communication Satellites 一种用于通信卫星的20W ka波段双端口功率放大器
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9963007
Chi Chen, Kuan Hu, Weilin Luo, K. Yin, Ruiyuan Kang, Ying Zhao, Fei Yang
{"title":"A 20W Ka-Band Dual-Port Power Amplifier for Communication Satellites","authors":"Chi Chen, Kuan Hu, Weilin Luo, K. Yin, Ruiyuan Kang, Ying Zhao, Fei Yang","doi":"10.1109/ICTA56932.2022.9963007","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963007","url":null,"abstract":"this paper presents a ka-band dual-port power amplifier, developed for low-orbit communication satellite. The power amplifier was designed based on 0.15 um gate length GaN MMIC power amplifiers. The RF output port is optional and controlled by external command. The maximum saturated power 25 W with a PAE of 33% has been achieved. The environmental tests for power amplifier have been carried out. The measured result and thermal vacuum test result have been shown in this paper. The power amplifier has been working well on-orbit for two years.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"758 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132913318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Proceedings of 2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) 2022年IEEE集成电路、技术与应用国际会议论文集
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/icta56932.2022.9963058
{"title":"Proceedings of 2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","authors":"","doi":"10.1109/icta56932.2022.9963058","DOIUrl":"https://doi.org/10.1109/icta56932.2022.9963058","url":null,"abstract":"","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123144159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation of Polynomial Fitted Poly-Harmonic Distortion Model with Frequency Defined Device 频率定义器件多项式拟合多谐失真模型的实现
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9963123
Xiaoqiang Tang, Jialin Cai
{"title":"Implementation of Polynomial Fitted Poly-Harmonic Distortion Model with Frequency Defined Device","authors":"Xiaoqiang Tang, Jialin Cai","doi":"10.1109/ICTA56932.2022.9963123","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963123","url":null,"abstract":"In this paper, a polynomial fitted poly-harmonic distortion (PHD) model is proposed, and it is implemented with frequency defined device (FDD). Polynomial fitting technique provides an effective method to including PHD model with different input power states through single set of model parameter. It can greatly reduce the model extraction complexity, and compact the model file size. The basic theory of PHD model, polynomial fitting method, and the FDD technique is provided in this work. A 10 W Gallium Nitride (GaN) packaged transistor is used in the test example. The results show that the proposed model has high accuracy for both fundamental and second harmonic behavioral predictions.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116154840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Memristor-based Digital Circuits for Realizing the Pavlov's Associative Neural Network 实现巴甫洛夫联想神经网络的忆阻器数字电路
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9962981
Yu Wang, Yi Liu, Jiayu Bao, Yu Yan, Ertao Hu, Xiang Wan, R. Xu, Haotong Zhang, Yi Tong
{"title":"Memristor-based Digital Circuits for Realizing the Pavlov's Associative Neural Network","authors":"Yu Wang, Yi Liu, Jiayu Bao, Yu Yan, Ertao Hu, Xiang Wan, R. Xu, Haotong Zhang, Yi Tong","doi":"10.1109/ICTA56932.2022.9962981","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962981","url":null,"abstract":"Memristors have sparked substantial interest in the hardware implementation of brain-inspired neuromorphic devices and systems. In this work, we propose a digital circuit to emulate the Pavlov's associative memory experiments based on fabricated Ag/TiO2/Pt memristors. Memristors operate as a logical signal processing unit in conjunction with the register to implement the emulation. The design of digital circuitry substantially increases the frequency of the system and reduces its power consumption and cost.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132197766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 0.3-µW,2.1-µVrms Neural Recording Chopper Amplifier with Low Noise DC-Servo-Loop 一个0.3µW,2.1µVrms的低噪声直流伺服回路神经记录斩波放大器
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9963006
Yuchen Bao, Weijian Chen, Zhixian Li, Yongsen Chen, Yanhan Zeng
{"title":"A 0.3-µW,2.1-µVrms Neural Recording Chopper Amplifier with Low Noise DC-Servo-Loop","authors":"Yuchen Bao, Weijian Chen, Zhixian Li, Yongsen Chen, Yanhan Zeng","doi":"10.1109/ICTA56932.2022.9963006","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963006","url":null,"abstract":"This paper presents a low noise and low power circuit for neural recording. A Capacitively-Coupled Chopper Instrumentation Amplifier (CCIA) with embedded DC feedback is proposed to reduce the noise of system. Implemented a continuous-time low-pass filter (LPF) at the output of the system and utilized bulk-feedback techniques to increase its output swing. Furthermore, the DC-block and Chopper-Capacitor-Chopper Integrator Based DC Servo Loop (C3IB-DSL) are combined to reduce the interferences. According to experiment, the circuit consumes only 0.3 µW at 1.2 V. In addition, the input-referred noise reached 2.1 µVrms and the noise efficiency factor (NEF) 3.6 at the same time. The proposed CCIA was simulated in a 180n CMOS process.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131194274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IPOCIM: Artificial Intelligent Processor with Adaptive Ping-pong Computing-in-Memory Architecture 具有自适应乒乓内存计算架构的人工智能处理器
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9963134
L. Chang, Chenglong Li, Xin Zhao, Shuisheng Lin, Jun Zhou
{"title":"IPOCIM: Artificial Intelligent Processor with Adaptive Ping-pong Computing-in-Memory Architecture","authors":"L. Chang, Chenglong Li, Xin Zhao, Shuisheng Lin, Jun Zhou","doi":"10.1109/ICTA56932.2022.9963134","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963134","url":null,"abstract":"Computing-in-memory (CIM) architecture is a promising solution toward energy-efficient artificial intelligent (AI) processor. Practically, the AI processor with CIM engine induces a series of issues including data updating and flexibility. For instance, in AI-oriented applications, the weight stored in the CIM must be reloaded due to the huge gap between limited capacity of CIM and growing weight parameter, which greatly reduces the computation efficiency of the AI processor. Moreover, the natural parallelism of CIM leads to the mismatch of various convolution kernel sizes in different networks and layers, which reduces hardware utilization efficiency. In this work, we explore a CIM engine with a ping-pong strategy as an alternative to traditional CIM macro and weight buffer, hiding the data update latency to enhance data reuse. In addition, we proposed a flexible CIM architecture adapting to different neural networks, namely IPOCIM, with a fine-grained data-flow mapping strategy. Based on the evaluation, IPOCIM achieves 1.4-7.1× performance improvement, and 2.2-6.1× energy efficiency, compared to baseline.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128764011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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