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2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)最新文献

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A Fast-Response BUCK Converter with Adaptive Detect and Transient Enhancement Techniques 基于自适应检测和瞬态增强技术的快速响应BUCK变换器
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2018-10-01 DOI: 10.1109/APCCAS.2018.8605610
Ze-kun Zhou, Junyuan Rong, Yue Shi, Bo Zhang
{"title":"A Fast-Response BUCK Converter with Adaptive Detect and Transient Enhancement Techniques","authors":"Ze-kun Zhou, Junyuan Rong, Yue Shi, Bo Zhang","doi":"10.1109/APCCAS.2018.8605610","DOIUrl":"https://doi.org/10.1109/APCCAS.2018.8605610","url":null,"abstract":"This paper presents a fast-response BUCK converter with adaptive transient detect technique (ATDT) and transient enhancement technique (TET). In order to reduce output overshoot and undershoot voltages and achieve shorter recovery time after load change, an adaptive transient detect module is adopted to determine one-shot transient response time, duty cycle will be set to 100% or 0% instantaneously and regulation speed of compensation capacitor voltage will be also enhanced during this time. Besides, oscillation issue is effectively avoided with proposed TET. The presented fast-response BUCK has been implemented in a 0.35μm BCD process, whose verified results are provided to demonstrate the stability and fast response of proposed converter. Compared with conventional BUCK converter, the transient response time is speeded up by more than 2.4X, and the overshoot voltage is shrunk by 0.64X while achieving 0.42X undershoot voltage.","PeriodicalId":325141,"journal":{"name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114656313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Switched Capacitor based High Positive and Negative Voltage Charge-pump using Sample and Hold technique 基于开关电容的高正负电压电荷泵，采用采样和保持技术
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2018-10-01 DOI: 10.1109/APCCAS.2018.8605637
V. Rana, A. Mittal
{"title":"Switched Capacitor based High Positive and Negative Voltage Charge-pump using Sample and Hold technique","authors":"V. Rana, A. Mittal","doi":"10.1109/APCCAS.2018.8605637","DOIUrl":"https://doi.org/10.1109/APCCAS.2018.8605637","url":null,"abstract":"A switched capacitor based high positive and negative voltage charge-pump using sample and hold technique is introduced. Circuit uses low voltage transistors, MOM capacitors and two-phase clock signals. As single circuit can generate both positive and negative voltages so we do not require huge on-chip capacitors separately for positive and negative charge-pump thus this circuit provides huge area saving. A self-timed clock is also generated to perform sample and hold process for this circuit. Another option is to use external clock for timing the sample and hold process. Circuit discuss about a single stage positive and negative voltage multiplier stage and four stage charge-pump system, which is designed and simulated in BCD-110nm technology with input supply of 2.5V. Circuit provides a voltage multiplication efficiency of 93% for positive voltage and 92% for negative voltages.","PeriodicalId":325141,"journal":{"name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117142769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 4K×2K@60fps Multi-format Multi-function Display Processor for High Perceptual Quality 一种4kx 2K@60fps高感知质量多格式多功能显示处理器
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2018-10-01 DOI: 10.1109/APCCAS.2018.8605706
Hang Wang, Hongbin Sun, Xuchong Zhang, Qiubo Chen, Pengju Ren, Xiaogang Wu, S. Yin, Zhiqian Jiang, Xiang Li, Daqiang Han, S. Yu, Shaojun Wei, Nanning Zheng
{"title":"A 4K×2K@60fps Multi-format Multi-function Display Processor for High Perceptual Quality","authors":"Hang Wang, Hongbin Sun, Xuchong Zhang, Qiubo Chen, Pengju Ren, Xiaogang Wu, S. Yin, Zhiqian Jiang, Xiang Li, Daqiang Han, S. Yu, Shaojun Wei, Nanning Zheng","doi":"10.1109/APCCAS.2018.8605706","DOIUrl":"https://doi.org/10.1109/APCCAS.2018.8605706","url":null,"abstract":"This paper presents a video display processor which supports a variety of video formats and integrates multiple advanced functions for image quality improvement, including edge-directed image upscaling, guided image filter (GIF) based detail enhancement and noise reduction, multi-view autostereoscopic 3D processing, etc. By leveraging algorithm and architecture co-design, this work efficiently implements these computational intensive display processing functions in a single chip. The chip is fabricated in GF 55nm CMOS technology, and the core size is 38.71mm2 including 1.8M logic gates and 541KB SRAM. The chip works at the maximum operating frequency of 594MHz with the core supply voltage of 1.2V. The maximum input and output video formats reach up to 4K×2K@60fps.","PeriodicalId":325141,"journal":{"name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127314639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 10-KS/s 625-Hz-Bandwidth 60-dB SNDR Noise-Shaping ADC for Bio-potential Signals Detection Application 用于生物电位信号检测的10-KS/s 625hz带宽60db SNDR噪声整形ADC
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2018-10-01 DOI: 10.1109/APCCAS.2018.8605701
Jin Hu, Maliang Liu, Shubin Liu, R. Ding, Zhangming Zhu
{"title":"A 10-KS/s 625-Hz-Bandwidth 60-dB SNDR Noise-Shaping ADC for Bio-potential Signals Detection Application","authors":"Jin Hu, Maliang Liu, Shubin Liu, R. Ding, Zhangming Zhu","doi":"10.1109/APCCAS.2018.8605701","DOIUrl":"https://doi.org/10.1109/APCCAS.2018.8605701","url":null,"abstract":"This paper presents a novel noise-shaping SAR ADC for bio-potential signal detection application. Its area and power consumption are greatly reduced compared to the conventional SAR ADC with the same effective number of bits. With the help of a proposed low power integrator, the comparator noise and quantization noise are greatly attenuated by 21dB in the band of interest. With such an aggressive attenuation, a 9.67-bit ENOB noise shaping SAR ADC can be achieved with a 7 bit DAC array. The prototype ADC is designed in 0.18μm CMOS process. Operating at 10KS/s, it consumes 73 nW from a 1-V supply. At an OSR of 8, the SAR ADC achieves a Walden figure of merit of 8.9 fJ/conversion-step, and its SNDR is 60dB.","PeriodicalId":325141,"journal":{"name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126854611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Novel Compiler for Regular Expression Matching Engine Construction 一种新的正则表达式匹配引擎编译器
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2018-10-01 DOI: 10.1109/APCCAS.2018.8605644
Xin Jin, Jun Lin, Zhongfeng Wang
{"title":"A Novel Compiler for Regular Expression Matching Engine Construction","authors":"Xin Jin, Jun Lin, Zhongfeng Wang","doi":"10.1109/APCCAS.2018.8605644","DOIUrl":"https://doi.org/10.1109/APCCAS.2018.8605644","url":null,"abstract":"Using regular expressions in intrusion detection systems (IDS) to represent some dangerous payload contents is a more efficient way than using invariant patterns. For each regular expression in regular expressions rules set a unique Nondeterministic Finite Automaton (NFA) structure is needed to be converted. It is crucial to implement a fast NFA construction. This paper presents a novel method for compiling large-scale regular expression matching engine (REME) on FPGA. We build an intelligent compiler for automatic converting regular expressions into register-transfer-level (RTL) using Verilog language, utilizing only logic slice available on FPGA because of the simple architecture used in the back-end of our compiler. Due to the independent converting method between the converting flow and the block structure, the compiler can easily change the single pattern structure to build the most advanced regular expression-matching engine (REME) which can fit the realistic demand. On a PC with a 3.3 GHz Intel i5-4590 processor and 4 GB memory, our compiler can convert more than one thousand regular expressions in less than 15 seconds. During the converting flow, the compiler provides an arbitrary match string and corresponding test bench file in Verilog as a part of the final output result.","PeriodicalId":325141,"journal":{"name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116526779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel Adaptive Rood Path Searches with Small Motion Prejudgments for Fast Block Motion Estimation 基于小运动预估的自适应路径搜索
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2018-10-01 DOI: 10.1109/APCCAS.2018.8605600
Hung-Yi Chen, Jian-Jiun Ding, Yih-Cherng Lee
{"title":"Novel Adaptive Rood Path Searches with Small Motion Prejudgments for Fast Block Motion Estimation","authors":"Hung-Yi Chen, Jian-Jiun Ding, Yih-Cherng Lee","doi":"10.1109/APCCAS.2018.8605600","DOIUrl":"https://doi.org/10.1109/APCCAS.2018.8605600","url":null,"abstract":"Block matching based motion estimation (BMME) is widely used in video compression and stereoscopic image processing. Given that the full search algorithm is not efficient enough, many fast motion estimation algorithms are based on BMME. Adaptive rood path search (ARPS), which is an important process of the BMME method, exploits the inter-block correlation and zero-motion prejudgment to reduce the search cost. Although ARPS is very efficient, there is a gap between ARPS and full search in accuracy. In this manuscript, we propose a novel adaptive rood path search (N-ARPS) algorithm with small-motion prejudgment (SMP). SMP is to select appropriate search strategy for each block according to its motion properties. In addition, region of support (ROS) expansion is applied to have a better prediction for the initial search. Experimental results show that the proposed fast search algorithm has a near-optimal search accuracy and extremely lower computational complexity when compared with standard-of-the-art algorithms.","PeriodicalId":325141,"journal":{"name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122387418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 0.65-V 10-bit 320-kS/s SAR-ADC with Charge Average and Skip Switching Algorithm 一种0.65 v 10位320-kS/s的SAR-ADC，具有电荷平均和跳跃切换算法
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2018-10-01 DOI: 10.1109/APCCAS.2018.8605716
Yi-Han Ou-Yang, Cheng-Chun Wu, K. Tang
{"title":"A 0.65-V 10-bit 320-kS/s SAR-ADC with Charge Average and Skip Switching Algorithm","authors":"Yi-Han Ou-Yang, Cheng-Chun Wu, K. Tang","doi":"10.1109/APCCAS.2018.8605716","DOIUrl":"https://doi.org/10.1109/APCCAS.2018.8605716","url":null,"abstract":"A high resolution and low power fully differential 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this work aiming at neural signal data acquisition. By utilizing surplus energy restored by MSB-split capacitors of alternative switching structure both in conversion phase and reset phase, the proposed charge average and skip switching algorithm achieves superior DAC switching energy efficiency without the requirement of an external Vcm reference. Implemented in 180nm CMOS process, the proposed chip occupied a 0.0564-mm2 core area. Operating at 320-kS/s sampling rate with 0.65-V supply voltage, it achieved an ENOB of 9.66-bit and FoM of 6.26 fJ/conv.-step. The measured DNL and INL results are within 0.29 LSB and 0.38 LSB, respectively.","PeriodicalId":325141,"journal":{"name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128746964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dolphin Recognition with Adaptive Hybrid Saliency Detection for Deep Learning Based on DenseNet Recognition 基于深度学习的自适应混合显著性检测海豚识别
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2018-10-01 DOI: 10.1109/APCCAS.2018.8605718
H. Hsu, Yih-Cherng Lee, Jian-Jiun Ding, Ronald Y. Chang
{"title":"Dolphin Recognition with Adaptive Hybrid Saliency Detection for Deep Learning Based on DenseNet Recognition","authors":"H. Hsu, Yih-Cherng Lee, Jian-Jiun Ding, Ronald Y. Chang","doi":"10.1109/APCCAS.2018.8605718","DOIUrl":"https://doi.org/10.1109/APCCAS.2018.8605718","url":null,"abstract":"Dolphin identification is important for wildlife conservation. Since identifying dolphins from thousands of images manually takes tremendous time, it is important to develop an automatic dolphin identification algorithm. In this paper, a high accurate deep learning based dolphin identification algorithm is proposed. We presented an advanced approach, called hybrid saliency method, for feature extraction and efficiently integrate several well-known techniques to make dolphins distinguishable. With the proposed techniques, we can avoid the background part (e.g. the sea water) to affect the identification results, which is usually a problem of most convolutional neural network based methods. Simulations show that the proposed algorithm can well identify a dolphin in most cases and it can achieve the accuracy rate of 85% even if there are 40 dolphins to be distinguished.","PeriodicalId":325141,"journal":{"name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126908659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Image Denoising Algorithms for DoFP Polarization Image Sensors with Non-Gaussian Noises 非高斯噪声DoFP偏振图像传感器的图像去噪算法
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2018-10-01 DOI: 10.1109/APCCAS.2018.8605608
B. Wang, Shiting Li, W. Ye, A. Abubakar, Xiaofang Pan, Xiaojin Zhao
{"title":"Image Denoising Algorithms for DoFP Polarization Image Sensors with Non-Gaussian Noises","authors":"B. Wang, Shiting Li, W. Ye, A. Abubakar, Xiaofang Pan, Xiaojin Zhao","doi":"10.1109/APCCAS.2018.8605608","DOIUrl":"https://doi.org/10.1109/APCCAS.2018.8605608","url":null,"abstract":"In this paper, we present four denoising algorithms dedicated to the division of focal plane (DoFP) polarization image sensors, including the average filtering, median filtering, Wiener filtering and wavelet threshold denoising algorithms. Compared with the previous implementations solely based on the Gaussian noise model, this paper, for the first time, covers the non-Gaussian noises, such as the salt & pepper noise and Poisson noise. According to our extensive experimental results, the wavelet threshold denoising outperforms for suppressing the Gaussian noise; while the median filtering and the Wiener filtering outperform for suppressing the low-density salt & pepper noise and Poisson noise, respectively.","PeriodicalId":325141,"journal":{"name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123526624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Security Path Verification Through Joint Information Flow Analysis 基于联合信息流分析的安全路径验证
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2018-10-01 DOI: 10.1109/APCCAS.2018.8605726
Wei Hu, Xinmu Wang, Dejun Mu
{"title":"Security Path Verification Through Joint Information Flow Analysis","authors":"Wei Hu, Xinmu Wang, Dejun Mu","doi":"10.1109/APCCAS.2018.8605726","DOIUrl":"https://doi.org/10.1109/APCCAS.2018.8605726","url":null,"abstract":"Security path verification is an effective measure for identifying design paths that can lead to security violations. However, existing techniques in this realm typically lack the flexibility in formal models for verification performance-precision tradeoffs and rely on new design languages and tools. In this paper, we propose a security path verification technique through joint information flow analysis. We formalize qualitative information flow models of different precision and complexity to enable verification performance tradeoffs. We further employ quantitative information flow metrics to assess the severity of identified security path violations. Our information flow models and security properties are described in standard HDL and property specification languages respectively, allowing verification to be performed using tools familiar to hardware designers. Experimental results show that our method is effective in identifying security vulnerabilities caused by design flaw, timing channel and hardware Trojan with verification performance benefits.","PeriodicalId":325141,"journal":{"name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114225196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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