Hang Wang, Hongbin Sun, Xuchong Zhang, Qiubo Chen, Pengju Ren, Xiaogang Wu, S. Yin, Zhiqian Jiang, Xiang Li, Daqiang Han, S. Yu, Shaojun Wei, Nanning Zheng
{"title":"一种4kx 2K@60fps高感知质量多格式多功能显示处理器","authors":"Hang Wang, Hongbin Sun, Xuchong Zhang, Qiubo Chen, Pengju Ren, Xiaogang Wu, S. Yin, Zhiqian Jiang, Xiang Li, Daqiang Han, S. Yu, Shaojun Wei, Nanning Zheng","doi":"10.1109/APCCAS.2018.8605706","DOIUrl":null,"url":null,"abstract":"This paper presents a video display processor which supports a variety of video formats and integrates multiple advanced functions for image quality improvement, including edge-directed image upscaling, guided image filter (GIF) based detail enhancement and noise reduction, multi-view autostereoscopic 3D processing, etc. By leveraging algorithm and architecture co-design, this work efficiently implements these computational intensive display processing functions in a single chip. The chip is fabricated in GF 55nm CMOS technology, and the core size is 38.71mm2 including 1.8M logic gates and 541KB SRAM. The chip works at the maximum operating frequency of 594MHz with the core supply voltage of 1.2V. The maximum input and output video formats reach up to 4K×2K@60fps.","PeriodicalId":325141,"journal":{"name":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 4K×2K@60fps Multi-format Multi-function Display Processor for High Perceptual Quality\",\"authors\":\"Hang Wang, Hongbin Sun, Xuchong Zhang, Qiubo Chen, Pengju Ren, Xiaogang Wu, S. Yin, Zhiqian Jiang, Xiang Li, Daqiang Han, S. Yu, Shaojun Wei, Nanning Zheng\",\"doi\":\"10.1109/APCCAS.2018.8605706\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a video display processor which supports a variety of video formats and integrates multiple advanced functions for image quality improvement, including edge-directed image upscaling, guided image filter (GIF) based detail enhancement and noise reduction, multi-view autostereoscopic 3D processing, etc. By leveraging algorithm and architecture co-design, this work efficiently implements these computational intensive display processing functions in a single chip. The chip is fabricated in GF 55nm CMOS technology, and the core size is 38.71mm2 including 1.8M logic gates and 541KB SRAM. The chip works at the maximum operating frequency of 594MHz with the core supply voltage of 1.2V. The maximum input and output video formats reach up to 4K×2K@60fps.\",\"PeriodicalId\":325141,\"journal\":{\"name\":\"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"volume\":\"130 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS.2018.8605706\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2018.8605706","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 4K×2K@60fps Multi-format Multi-function Display Processor for High Perceptual Quality
This paper presents a video display processor which supports a variety of video formats and integrates multiple advanced functions for image quality improvement, including edge-directed image upscaling, guided image filter (GIF) based detail enhancement and noise reduction, multi-view autostereoscopic 3D processing, etc. By leveraging algorithm and architecture co-design, this work efficiently implements these computational intensive display processing functions in a single chip. The chip is fabricated in GF 55nm CMOS technology, and the core size is 38.71mm2 including 1.8M logic gates and 541KB SRAM. The chip works at the maximum operating frequency of 594MHz with the core supply voltage of 1.2V. The maximum input and output video formats reach up to 4K×2K@60fps.