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Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)最新文献

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Platform-scalable Task Partition and Multilevel Buffering in Multi-processor Plessey Corner Detector 多处理器Plessey角检测器中平台可扩展任务分区和多级缓冲
Seventh International Conference on Application of Concurrency to System Design (ACSD 2007) Pub Date : 2007-07-10 DOI: 10.1109/ACSD.2007.58
Guan Yu, G. Lafruit, P. Schelkens
{"title":"Platform-scalable Task Partition and Multilevel Buffering in Multi-processor Plessey Corner Detector","authors":"Guan Yu, G. Lafruit, P. Schelkens","doi":"10.1109/ACSD.2007.58","DOIUrl":"https://doi.org/10.1109/ACSD.2007.58","url":null,"abstract":"The Plessey corner detector is a key technological component in scene analysis, stereo matching, and object tracking. Due to its high computation complexity, earlier fast implementations mainly focused on hardware implementations. This paper explores the viability of a multi-processor software implementation. A scalable task partitioning for efficiently mapping the Plessey algorithm on a multi-processor platform is proposed. The task partition ensures platform scalability, low inter-processor communication overhead and a well-balanced workload in each task. In addition, a multilevel buffering scheme is presented, minimizing the external memory accesses in each task to one image pixel read per calculated corner response value. The effectiveness of the proposed task partition and buffering scheme has been verified on (i) a cycle accurate simulator with shared memory and (ii) a multiple-TI-C64 DSP board using a message passing paradigm. The proposed solution combines good platform scalability with an additional 30% speedup gain over straightforward parallelization schemes.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120971219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The Design of Virtual Self-timed Block for Activity Communication in SOC SOC中活动通信的虚拟自定时块设计
Seventh International Conference on Application of Concurrency to System Design (ACSD 2007) Pub Date : 2007-07-10 DOI: 10.1109/ACSD.2007.74
Yuan Chen, Fei Xia, D. Shang, A. Yakovlev
{"title":"The Design of Virtual Self-timed Block for Activity Communication in SOC","authors":"Yuan Chen, Fei Xia, D. Shang, A. Yakovlev","doi":"10.1109/ACSD.2007.74","DOIUrl":"https://doi.org/10.1109/ACSD.2007.74","url":null,"abstract":"In this paper we present the architecture for virtual self-timed blocks. Being globally asynchronous locally synchronous (GALS) and lazy reactive processing units, such blocks target multi-processing on-chip systems where power consumption is an important factor. The architecture provides a hardware foundation which transparently supports the systematic organization of application-level activities (processes) and the efficient use of system resources. It further facilitates the seamless integration of IP cores into systems by enhancing the GALS paradigm and protecting clocked IP cores from the temporal nondeterminism in their environments. This work includes the basic design of the virtual self-timed block architecture, Matlab models of the important components involved, and demonstrative analyses in Matlab.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126897004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Asynchronous Data Path Models 异步数据路径模型
Seventh International Conference on Application of Concurrency to System Design (ACSD 2007) Pub Date : 2007-07-10 DOI: 10.1109/ACSD.2007.45
D. Sokolov, I. Poliakov, A. Yakovlev
{"title":"Asynchronous Data Path Models","authors":"D. Sokolov, I. Poliakov, A. Yakovlev","doi":"10.1109/ACSD.2007.45","DOIUrl":"https://doi.org/10.1109/ACSD.2007.45","url":null,"abstract":"A token-based model for asynchronous data path is formally defined and three token game semantics, spread token, antitoken and counterflow, are introduced. These semantics are studied and their advantages and drawbacks are highlighted. For analysis and comparison a software tool is developed which integrates these models into a consistent framework. The models are verified by mapping them into Petri nets and employing the existing model checking tools.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129900351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A more efficient time Petri net state space abstraction preserving linear properties 一个更有效的时间Petri网状态空间抽象，保持线性性质
Seventh International Conference on Application of Concurrency to System Design (ACSD 2007) Pub Date : 2007-07-10 DOI: 10.1109/ACSD.2007.41
H. Boucheneb, Hind Rakkay
{"title":"A more efficient time Petri net state space abstraction preserving linear properties","authors":"H. Boucheneb, Hind Rakkay","doi":"10.1109/ACSD.2007.41","DOIUrl":"https://doi.org/10.1109/ACSD.2007.41","url":null,"abstract":"We consider here time Petri nets (TPN model). We first propose an abstraction to its generally infinite state space which preserves linear properties of the TPN model. Comparing with TPN abstractions proposed in the literature, our abstraction produces graphs which are both smaller and faster to compute. In addition, our characterization of abstracted states allows a significative gain in space. Afterwards, we show how to apply Yoneda's partial order reduction technique to construct directly reduced graphs useful to verify LTL-X properties of the model. Using our approach, both time and space complexities are significantly reduced.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122072356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Finding Structure in Unstructured Processes: The Case for Process Mining 在非结构化过程中发现结构:过程挖掘的案例
Seventh International Conference on Application of Concurrency to System Design (ACSD 2007) Pub Date : 2007-07-10 DOI: 10.1109/ACSD.2007.50
Wil M.P. van der Aalst, C. Günther
{"title":"Finding Structure in Unstructured Processes: The Case for Process Mining","authors":"Wil M.P. van der Aalst, C. Günther","doi":"10.1109/ACSD.2007.50","DOIUrl":"https://doi.org/10.1109/ACSD.2007.50","url":null,"abstract":"Today there are many process mining techniques that allow for the automatic construction of process models based on event logs. Unlike synthesis techniques (e.g., based on regions), process mining aims at the discovery of models (e.g., Petri nets) from incomplete information (i.e., only example behavior is given). The more mature process mining techniques perform well on structured processes. However, most of the existing techniques fail miserably when confronted with unstructured processes. This paper attempts to \"bring structure to the unstructured\" by using an integrated combination of abstraction and clustering techniques. The ultimate goal is to present process models that are understandable by analysts and that lead to improved system/process redesigns.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115420591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 129
Modelling Mobility in High-level Petri Nets 高级Petri网的流动性建模
Seventh International Conference on Application of Concurrency to System Design (ACSD 2007) Pub Date : 2007-07-10 DOI: 10.1109/ACSD.2007.55
Raymond R. Devillers, Hanna Klaudel, M. Koutny
{"title":"Modelling Mobility in High-level Petri Nets","authors":"Raymond R. Devillers, Hanna Klaudel, M. Koutny","doi":"10.1109/ACSD.2007.55","DOIUrl":"https://doi.org/10.1109/ACSD.2007.55","url":null,"abstract":"We propose a structural translation of terms from a variant of the KLAIM process algebra which includes arbitrary tuples of data values as well as conditionals into behaviourally equivalent high-level Petri nets. This defines a semantics for mobility allowing one to deal directly with concurrency and causality.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"56 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131609898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Hazard Checking of Timed Asynchronous Circuits Revisited 再论定时异步电路的危害检查
Seventh International Conference on Application of Concurrency to System Design (ACSD 2007) Pub Date : 2007-07-10 DOI: 10.1109/ACSD.2007.52
Frédéric Béal, T. Yoneda, C. Myers
{"title":"Hazard Checking of Timed Asynchronous Circuits Revisited","authors":"Frédéric Béal, T. Yoneda, C. Myers","doi":"10.1109/ACSD.2007.52","DOIUrl":"https://doi.org/10.1109/ACSD.2007.52","url":null,"abstract":"This paper proposes a new approach for the hazard checking of timed asynchronous circuits. Previous papers proposed either exact algorithms, which suffer from statespace explosion, or efficient algorithms which use a (conservative) approximation to avoid state-space explosion but can result in the rejection of designs which are valid. In particular, [7] presents a timed extention of the work in [1] which is very efficient but is not able to handle circuits with internal loops, which prevents its use in some cases. We propose a new approach to the problem in order to overcome the mentioned limitations, without sacrificing efficiency. To do so, we first introduce a general framework targeted at the conservative checking of safety failures. This framework is not restricted to the checking of timed asynchronous circuits. Secondly, we propose a new (conservative) semantics for timed circuits, in order to use the proposed framework for hazard checking of such circuits. Using this framework with the proposed semantics yields an efficient algorithm that addresses the limitations of the previous approaches.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128344278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Mapping Applications to Tiled Multiprocessor Embedded Systems 映射应用到平铺多处理器嵌入式系统
Seventh International Conference on Application of Concurrency to System Design (ACSD 2007) Pub Date : 2007-07-10 DOI: 10.1109/ACSD.2007.53
L. Thiele, Iuliana Bacivarov, Wolfgang Haid, Kai Huang
{"title":"Mapping Applications to Tiled Multiprocessor Embedded Systems","authors":"L. Thiele, Iuliana Bacivarov, Wolfgang Haid, Kai Huang","doi":"10.1109/ACSD.2007.53","DOIUrl":"https://doi.org/10.1109/ACSD.2007.53","url":null,"abstract":"Modern multiprocessor embedded systems execute a large number of tasks on shared processors and handle their complex communications on shared communication networks. Traditional methods from the HW /SW codesign or general purpose computing domain cannot be applied any more to cope with this new class of complex systems. To overcome this problem, a framework called Distributed Operation Layer (DOL) is proposed that enables the efficient execution of parallel applications on multiprocessor platforms. Two main services are offered by the DOL: systemlevel performance analysis and multi-objective algorithmarchitecture mapping. This paper presents the basic principles of the DOL, the specification mechanisms for applications, platform and mapping as well as its internal analytic performance evaluation framework. To illustrate the presented concepts, an MPEG -2 decoder case study is presented.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114415132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 196
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