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2009 27th IEEE VLSI Test Symposium最新文献

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Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions 基于函数的路径延迟故障可伸缩压缩测试模式生成
2009 27th IEEE VLSI Test Symposium Pub Date : 2009-05-03 DOI: 10.1109/VTS.2009.22
E. Flanigan, S. Tragoudas, Arkan Abdulrahman
{"title":"Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions","authors":"E. Flanigan, S. Tragoudas, Arkan Abdulrahman","doi":"10.1109/VTS.2009.22","DOIUrl":"https://doi.org/10.1109/VTS.2009.22","url":null,"abstract":"A recent decision diagram-based algorithm [12] was able to generate test patterns for each sensitizable path delay fault. Although scalable this approach results to prohibitively long test sets. This paper presents a novel technique to intelligently select paths for compaction. It guarantees optimal compaction subject to the order of processing faults. The compaction rate is superior to any published method, even for the small benchmarks where enumerative compaction methods have been proposed. Experimental results on the publicly available benchmarks demostrate the scalability of the proposed method.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114430499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A New Post-Silicon Debug Approach Based on Suspect Window 一种基于可疑窗口的后硅调试新方法
2009 27th IEEE VLSI Test Symposium Pub Date : 2009-05-03 DOI: 10.1109/VTS.2009.35
Jianliang Gao, Yinhe Han, Xiaowei Li
{"title":"A New Post-Silicon Debug Approach Based on Suspect Window","authors":"Jianliang Gao, Yinhe Han, Xiaowei Li","doi":"10.1109/VTS.2009.35","DOIUrl":"https://doi.org/10.1109/VTS.2009.35","url":null,"abstract":"Bugs are tending to be unavoidable in the design of complex integrated circuits. It is imperative to identify the bugs as soon as possible by post-silicon debug. The main challenge for post-silicon debug is the observability of the internal signals. This paper exploits the fact that it is not necessary to observe the error free states. Then we introduce \"suspect window\" and present a method for determining its boundary. Based on suspect window, we propose a debug approach to achieve high observability by reusing scan chain. Since scan dumps take place only in suspect window, debug time is greatly reduced. Experiment results demonstrate the effectiveness of the proposed approach.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133481799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Automatic Selection of Internal Observation Signals for Design Verification 设计验证内部观测信号的自动选择
2009 27th IEEE VLSI Test Symposium Pub Date : 2009-05-03 DOI: 10.1109/VTS.2009.21
Tao Lv, Huawei Li, Xiaowei Li
{"title":"Automatic Selection of Internal Observation Signals for Design Verification","authors":"Tao Lv, Huawei Li, Xiaowei Li","doi":"10.1109/VTS.2009.21","DOIUrl":"https://doi.org/10.1109/VTS.2009.21","url":null,"abstract":"As the design complexity increases dramatically, results of functional simulation are usually checked through only a part of signals during design verification. It is important, therefore, to consider the observability of internal signals for effective checking. This paper proposes a static observability analysis method to automatically select internal observation signals, which improves the quality of functional verification. A series of formulas are defined to evaluate observability of internal signals, and an algorithm is proposed to locate the sources of low-observability. Such sources, rather than general hard-to-observe signals, are desirable internal observation signals. Experimental results indicate that signals selected by this method can improve the observability of designs more than those randomly selected from hard-to-observe signals.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124231450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Efficient Scheduling of Path Delay Tests for Latch-Based Circuits 基于锁存电路的路径延迟测试的有效调度
2009 27th IEEE VLSI Test Symposium Pub Date : 2009-05-03 DOI: 10.1109/VTS.2009.41
K. Chung, S. Gupta
{"title":"Efficient Scheduling of Path Delay Tests for Latch-Based Circuits","authors":"K. Chung, S. Gupta","doi":"10.1109/VTS.2009.41","DOIUrl":"https://doi.org/10.1109/VTS.2009.41","url":null,"abstract":"In many high-speed parts of chips, latch-based circuits are used to enable time borrowing, where a block may take longer time than its nominal delay to complete its computation. This enables such circuits to attain high performance and yield. In [1] and [2], we focused on maximizing path delay fault coverage and proposed the first structural delay testing approach and the associated design-for-testability (DFT) for such circuits. This approach provides dramatically higher coverage of path delay faults.In this paper, we focus on minimizing test application cost for delay testing latch-based circuits while ensuring that maximum coverage is achieved. We show that conventional test scheduling methods may not be applicable due to the unique characteristics of latch-based circuits with time borrowing. We then formulate the minimization problem and propose two heuristic approaches. The experimental results show that, for many example circuits, the proposed approaches achieve overall test application costs that are within 5% of the corresponding lower-bounds.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130139673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller 现代微处理器控制器中RT级与门级故障的指令级影响比较
2009 27th IEEE VLSI Test Symposium Pub Date : 2009-05-03 DOI: 10.1109/VTS.2009.32
M. Maniatakos, Naghmeh Karimi, C. Tirumurti, A. Jas, Y. Makris
{"title":"Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller","authors":"M. Maniatakos, Naghmeh Karimi, C. Tirumurti, A. Jas, Y. Makris","doi":"10.1109/VTS.2009.32","DOIUrl":"https://doi.org/10.1109/VTS.2009.32","url":null,"abstract":"We discuss the results of an extensive fault simulation study involving the control logic of a modern Alpha-like microprocessor. In this comparative study, faults are injected in both the RT- and the Gate-Level description of the design and are simulated under actual workload of the microprocessor, which is executing SPEC2000 benchmarks. The objective of this study is to analyze and contrast the impact of RT- and Gate-Level faults on the instruction execution flow of the microprocessor. The key observation is a pronounced consistency in the type and frequency of Instruction Level Errors (ILEs) arising due to RT- vs. Gate-Level faults. The motivation for this work stems from the need to understand the relative importance of low-level faults based on their instruction-level impact, in order to appropriately allocate error detection and/or correction resources. Hence, the consistency revealed through this study implies that such decisions can be made equally effective based on RT-Level fault simulation results, as with their far more computationally-expensive Gate-Level equivalents.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127934142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Recursive Path Selection for Delay Fault Testing 延迟故障测试的递归路径选择
2009 27th IEEE VLSI Test Symposium Pub Date : 2009-05-03 DOI: 10.1109/VTS.2009.50
Jaeyong Chung, J. Abraham
{"title":"Recursive Path Selection for Delay Fault Testing","authors":"Jaeyong Chung, J. Abraham","doi":"10.1109/VTS.2009.50","DOIUrl":"https://doi.org/10.1109/VTS.2009.50","url":null,"abstract":"This paper presents a new path selection algorithm for delay fault testing in a statistical timing framework. Existing algorithms which consider correlation between paths use an iterative process for each path or defect and require a Monte Carlo simulation for each iteration to calculate the conditional fault probability. The proposed algorithm does not require the iteration process and selects a requested number of paths simultaneously once it performs a statistical timing analysis at the beginning. If selection of k paths is required in a set of paths, it partitions the set into two path sets and determines how many paths should be selected in each path set out of the k paths. It recursively continues this process and ends up with k paths. The partitioning is easily performed during the recursive traversal of a circuit, which produces an imaginary path tree, where paths are already grouped based on their prefix. Experimental results show the proposed algorithm can effectively use structural correlation and spatial correlation to generate high quality path sets.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129300815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification 基于RTL不在乎路径识别的延迟故障过度测试综合缓解方法
2009 27th IEEE VLSI Test Symposium Pub Date : 2009-05-03 DOI: 10.1109/VTS.2009.27
Yuki Yoshikawa, S. Ohtake, Tomoo Inoue, H. Fujiwara
{"title":"A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification","authors":"Yuki Yoshikawa, S. Ohtake, Tomoo Inoue, H. Fujiwara","doi":"10.1109/VTS.2009.27","DOIUrl":"https://doi.org/10.1109/VTS.2009.27","url":null,"abstract":"A register-transfer level (RTL) circuit meeting a design specification may contain some functionally unused paths.If functionally unused paths can be easily identified at RTL,the information can be utilized to eliminate the corresponding gate-level paths from the target of testing.Testing such gate-level paths is considered to be futile. In this paper, we present a method for identifying such functionally unused paths, called RTL don't care paths, using RTL information, and a method of synthesis for transforming the identified paths into untestable paths which will never do a mischief.As a result, our approaches contribute to identification of many untestable paths and reduction of over-testing.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121686507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
RT-Level Deviation-Based Grading of Functional Test Sequences 基于rt水平偏差的功能测试序列分级
2009 27th IEEE VLSI Test Symposium Pub Date : 2009-05-03 DOI: 10.1109/VTS.2009.12
Hongxia Fang, K. Chakrabarty, A. Jas, S. Patil, C. Tirumurti
{"title":"RT-Level Deviation-Based Grading of Functional Test Sequences","authors":"Hongxia Fang, K. Chakrabarty, A. Jas, S. Patil, C. Tirumurti","doi":"10.1109/VTS.2009.12","DOIUrl":"https://doi.org/10.1109/VTS.2009.12","url":null,"abstract":"Functional test sequences are often used in manufacturing testing to target defects that are not detected by structural test. Therefore, it is necessary to evaluate the quality of functional test sequences. However, it is very time-consuming to evaluate the quality of functional test sequences by gate-level fault simulation. Therefore, we propose output deviations as a metric to grade functional test sequences at the register transfer (RT)-level without explicit fault simulation. Experimental results for the open-source Parwan processor and the Scheduler module of the Illinois Verilog Model (IVM) show that the deviations metric is computationally ef¿cient and it correlates well with gate-level coverage for stuck-at, transition-delay, and bridging faults. Results also show that functional test sequences that are reordered based on output deviations provide steeper gate-level fault coverage ramp-up compared to other ordering methods.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129920039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Experimental Validation of a BIST Techcnique for CMOS Active Pixel Sensors CMOS有源像素传感器的BIST技术实验验证
2009 27th IEEE VLSI Test Symposium Pub Date : 2009-05-03 DOI: 10.1109/VTS.2009.30
L. Lizarraga, S. Mir, G. Sicard
{"title":"Experimental Validation of a BIST Techcnique for CMOS Active Pixel Sensors","authors":"L. Lizarraga, S. Mir, G. Sicard","doi":"10.1109/VTS.2009.30","DOIUrl":"https://doi.org/10.1109/VTS.2009.30","url":null,"abstract":"In this paper we present the experimental evaluation of a Built-In-Self-Test (BIST) principle for the detection of defective pixels of a CMOS imager. The pixel BIST technique aims at an structural test based on electrical stimuli. Simple electrical test measures are considered. Test limits are set in order to minimize pixel false acceptance and false rejection under mismatch deviations. The pixel BIST is next evaluated by considering the fault coverage obtained with catastrophic and single parametric faults. Finally, test metrics obtained by simulation for mismatch deviations are compared with experimental data.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128861004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A Scalable, Digital BIST Circuit for Measurement and Compensation of Static Phase Offset 一种用于静态相位偏移测量和补偿的可扩展数字BIST电路
2009 27th IEEE VLSI Test Symposium Pub Date : 2009-05-03 DOI: 10.1109/VTS.2009.36
K. Jenkins, Lionel Li
{"title":"A Scalable, Digital BIST Circuit for Measurement and Compensation of Static Phase Offset","authors":"K. Jenkins, Lionel Li","doi":"10.1109/VTS.2009.36","DOIUrl":"https://doi.org/10.1109/VTS.2009.36","url":null,"abstract":"An on-chip circuit to measure static phase offset between a reference signal and the feedback signal of a PLL (phase-locked loop) is designed using only digital elements. It is demonstrated in a 65 nm, 1.0 V CMOS technology. It has a measured resolution of 2ps and a range of more than +/- 100ps of phase offset and, and consumes 3mW of power at 1 GHz. It uses an on-chip calibration referred to the reference clock frequency. The measured results are reported through digital scan chains.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130270336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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