2009 27th IEEE VLSI Test Symposium最新文献

{"title":"An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects","authors":"N. Houarche, M. Comte, M. Renovell, A. Czutro, P. Engelke, I. Polian, B. Becker","doi":"10.1109/VTS.2009.57","DOIUrl":"https://doi.org/10.1109/VTS.2009.57","url":null,"abstract":"In this paper a new electrical model is proposed to be used in fault size based fault simulation of crosstalk aggravated resistive short defects. The electrical behavior of the defect is first described and analyzed in details. Then an electrical model is proposed allowing to efficiently compute the critical resistance determining the range of detectable short resistance. The model is validated by comparison with SPICE simulations.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114679299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"False Path Aware Timing Yield Estimation under Variability","authors":"Lin Xie, A. Davoodi, K. Saluja, Abhishek A. Sinkar","doi":"10.1109/VTS.2009.17","DOIUrl":"https://doi.org/10.1109/VTS.2009.17","url":null,"abstract":"Effects of fluctuations in circuit timing due to process and environmental variations are becoming increasingly important as we move into sub-45nm technology. Since the delay of each gate is dependent on its input vectors, the timing yield, the probability that the circuit meets the given timing constraint, varies with different primary input patterns. Traditional timing yield estimation approaches assumed worst case delay models for each gate over all its input vectors, which results in much pessimism. To overcome the aforementioned problems, this paper proposes a Monte Carlo based approach which can obtain a much tighter lower bound on the circuit timing yield compared to the existing timing yield estimation techniques. Specifically, our approach builds multiple input-vector-dependent variation-aware delay models for each logic gate, and considers the impact of false paths, both static and dynamic false paths, which are carefully selected from the likely timing-critical paths under variability. We demonstrate gradual improvement in the estimated timing yield in the simulation results, and show that the timing yield computed using traditional worst-case delay models is highly pessimistic.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125939548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Panel: Functional Verification Planning and Management - Are Good Intentions Good Enough?","authors":"Andrew Piziali","doi":"10.1109/VTS.2009.66","DOIUrl":"https://doi.org/10.1109/VTS.2009.66","url":null,"abstract":"This panel will debate the efficacy of state-of-the-art techniques and methodologies that are becoming more widely used in industry today for planning, monitoring and assessing verification progress. Some panelists will argue planning, monitoring and assessment of the verification process are essential for predictable, successful verification. They claim quantifying the scope of the verification problem, specifying its solution and measuring verification progress against this plan dramatically reduces schedule uncertainty and provides an adaptive framework for accommodating design and schedule changes. Other panelists may argue this degree of rigor is an academic approach with little payoff in industrial designs and, in fact, its opportunity cost eclipses more rapid functional closure approaches.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128761161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Panel: Analog Characterization and Test: The Long Road to Realization","authors":"Arani Sinha, Amitava Majumdar, Vasu Ganti","doi":"10.1109/VTS.2009.65","DOIUrl":"https://doi.org/10.1109/VTS.2009.65","url":null,"abstract":"","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129128733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Special Session 11C: Embedded Tutorial: System-on-a-Chip Power Management Implications on Validation and Testing","authors":"B. Kapoor","doi":"10.1109/VTS.2009.64","DOIUrl":"https://doi.org/10.1109/VTS.2009.64","url":null,"abstract":"We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power consumption has become one of the most important differentiating factors for semiconductor products due to a major shift in the market towards handheld consumer devices. Power is a primary design criterion for bulk of the semiconductor designs now. Power is a key reason behind the shift towards multi-core designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115043222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Microscale and Nanoscale Thermal Characterization of Integrated Circuit Chips","authors":"B. Courtois, A. Shakouri","doi":"10.1109/VTS.2009.73","DOIUrl":"https://doi.org/10.1109/VTS.2009.73","url":null,"abstract":"An overview of various microscale and nanoscale thermal characterization techniques is presented (1-3). After a brief introduction to conventional micro thermocouples, various contact and contactless techniques will be reviewed. Infrared microscopy is based on thermal emission and it is a convenient technique that could be used with features tens of microns in size. Resolution limits due to low emissivity and transparency of various materials and issues related to background radiation will be discussed (3). Liquid crystals that change color have been widely used for hot spot identification in integrated circuit chips. Very high thermal sensitivity near the phase transition temperature is achieved. The main problems are related to calibration and aging of the liquid crystal. Micro Raman is an optical method that can be used to measure absolute temperature as well as the amount of the stress in the material. Micron spatial resolution with several degrees temperature resolution as well as 3D imaging has been achieved (4). Recent micro Raman characterization of GaN high power transistors will be reviewed. Thermoreflectance technique is based on the change of the sample reflection coefficient as a function of temperature. This small change in 10 -4 -10 -5 range per degree is typically detected using lock-in technique when the temperature of the device is cycled (1-3,5). Use of visible and near IR wavelengths allows both top surface and through the substrate measurement (6,7). Both single point measurements using a scanning laser and imaging with CCD or specialized lock-in cameras have been demonstrated. Recent advances for transient thermal imaging with sub microsecond time resolution is presented (8,9). For ultrafast thermal decay measurement, pump-probe technique using nanosecond or femtosecond lasers have been demonstrated. This is typically used to measure thin film thermal diffusivity and thermal interface resistance (10,11). The spatial resolution of various optical techniques can be improved with the use of tapered- fibers and near field scanning microscopy (12). While sub diffraction limit structures have been detected, strong attenuation of the signal reduces the temperature resolution significantly. Scanning thermal microscopy which is based on nanoscale thermocouples at the tip of atomic force microscope has had success in ultra high spatial resolution thermal mapping (13). Issues related to thermal resistance between the tip and the sample and parasitic heat transfer paths will be discussed. ACKNOWLEDGMENT","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123206593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Packet Based 2x-Site Test Solution for GSM Transceivers with Limited Tester Resources","authors":"E. Erdogan, S. Ozev","doi":"10.1109/VTS.2009.44","DOIUrl":"https://doi.org/10.1109/VTS.2009.44","url":null,"abstract":"In this paper, we present a 2x-site test solution for GSM transceivers using only baseband signals for analysis. We perform all operations on standard-compliant GSM packets, thereby putting the device under the normal operating conditions. The transmitter on one device under test (DUT) is coupled with a receiver on another DUT to form a complete Tx-Rx path. Parameters of the two devices are decoupled from one another by carefully modeling the system into a known format and using signal processing techniques. Simulation as well as measurement results confirm the high accuracy of the proposed technique.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125567461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Time Domain Method to Measure Oscillator Phase Noise","authors":"Kenneth Blakkan, M. Soma","doi":"10.1109/VTS.2009.54","DOIUrl":"https://doi.org/10.1109/VTS.2009.54","url":null,"abstract":"Time domain measurement of a real oscillator output   reveals non-ideal variation, commonly called jitter. This paper presents a new measurement method to test for the presence of a phase noise spur in an oscillator’s output. Models for some specific classes of jitter characterize noise in the time domain, namely: random jitter (RJ); and a sub-class of deterministic jitter (DJ), sinusoidal jitter (SJ).  These models and analysis of m-cycle-to-m-cycle jitter enable estimation of phase noise power spectral density characteristics for an oscillators output. Specifically, m-cycle-to-m-cycle jitter extracted from time domain measurements characterize SNR for discrete spurious phase noise. Thus, this method uses time domain measurements to estimate the effect of real noise sources, such as digital switching noise that couples to the oscillator output, and appears as phase noise spurs in the frequency domain.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122236656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Predictive Test Technique for Diagnosis of RF CMOS Receivers","authors":"K. Suenaga, S. Bota, R. Picos, E. Isern, M. Roca, E. García-Moreno","doi":"10.1109/VTS.2009.13","DOIUrl":"https://doi.org/10.1109/VTS.2009.13","url":null,"abstract":"In this paper, a sequential test technique is proposed to test a RF front-end receiver. With this technique the test circuitry can be reused by the receiver building blocks.The method is suitable to be fully integrated On-Chip. Moreover, the test area overhead has been kept low by using the receiver LO in the test circuitry. Therefore the test circuitry required to generate the test stimuli are an IF generator and an auxiliary mixer. The above technique has been combined with a test strategy based on the estimation of selected performance parameters of the receiver building blocks. These estimations are done by using easily measurable test observables as DC supply current consumption. RMS estimation errors for the gain and the 1dB compression point of the LNA and the down converter in the receiver chain are all below 2 %.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122306203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dynamic Test Compaction for Transition Faults in Broadside Scan Testing Based on an Influence Cone Measure","authors":"D. Xiang, Boxue Yin, K. Cheng","doi":"10.1109/VTS.2009.14","DOIUrl":"https://doi.org/10.1109/VTS.2009.14","url":null,"abstract":"We propose a compact test generation method for transition faults, which is driven by a conflict-avoidance scheme employed during test generation. Based on an influence-cone function for transition faults in broadside scan testing, two dynamic test compaction schemes, named selfish test compaction and unselfish test compaction respectively, are proposed. The selfish test compaction tries to compact as many faults as possible into the current test, while the unselfish scheme attempts to compact the tests of the hard-to-compact faults into the current test. Potential conflicts produced by the signal requirements at the pseudo-primary outputs in the first frame are avoided through the use of an input dependency graph. Experimental results and comparison with existing approaches demonstrate the efficiency and effectiveness of the proposed method.","PeriodicalId":323554,"journal":{"name":"2009 27th IEEE VLSI Test Symposium","volume":"76 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116564479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}