(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE最新文献_第3页

Scalable, accurate multicore simulation in the 1000-core era 可扩展的，精确的多核模拟在1000核时代

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762734

Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, O. Khan, S. Devadas

{"title":"Scalable, accurate multicore simulation in the 1000-core era","authors":"Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, O. Khan, S. Devadas","doi":"10.1109/ISPASS.2011.5762734","DOIUrl":"https://doi.org/10.1109/ISPASS.2011.5762734","url":null,"abstract":"We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based on an ingress-queued worm-hole router NoC architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization; while preserving functional accuracy, this permits tradeoffs between perfect timing accuracy and high speed with very good accuracy. When run on 6 separate physical cores on a single die, speedups can exceed a factor of over 5, and when run on a two-die 12-core system with 2-way hyperthreading, speedups exceed 11 ×. Most hardware parameters are configurable, including memory hierarchy, interconnect geometry, bandwidth, crossbar dimensions, and parameters driving power and thermal effects. A highly parametrized table-based NoC design allows a variety of routing and virtual channel allocation algorithms out of the box, ranging from simple DOR routing to complex Valiant, ROMM, or PROM schemes, BSOR, and adaptive routing. HORNET can run in network-only mode using synthetic traffic or traces, directly emulate a MIPS-based multicore, or function as the memory subsystem for native applications executed under the Pin instrumentation tool. HORNET is freely available under the open-source MIT license at http://csg.csail.mit.edu/hornet/.","PeriodicalId":323366,"journal":{"name":"(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116479729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 73

Performance evaluation of adaptivity in software transactional memory 软件事务性内存自适应性能评价

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762733

Mathias Payer, T. Gross

{"title":"Performance evaluation of adaptivity in software transactional memory","authors":"Mathias Payer, T. Gross","doi":"10.1109/ISPASS.2011.5762733","DOIUrl":"https://doi.org/10.1109/ISPASS.2011.5762733","url":null,"abstract":"Transactional memory (TM) is an attractive platform for parallel programs, and several software transactional memory (STM) designs have been presented. We explore and analyze several optimization opportunities to adapt STM parameters to a running program. This paper uses adaptSTM, a flexible STM library with a non-adaptive baseline common to current fast STM libraries to evaluate different performance options. The baseline is extended by an online evaluation system that enables the measurement of key runtime parameters like read- and write-locations, or commit- and abort-rate. The performance data is used by a thread-local adaptation system to tune the STM configuration. The system adapts different important parameters like write-set hash-size, hash-function, and write strategy based on runtime statistics on a per-thread basis. We discuss different self-adapting parameters, especially their performance implications and the resulting trade-offs. Measurements show that local per-thread adaptation outperforms global system-wide adaptation. We position local adaptivity as an extension to existing systems. Using the STAMP benchmarks, we compare adaptSTM to two other STM libraries, TL2 and tinySTM. Comparing adaptSTM and the adaptation system to TL2 results in an average speedup of 43% for 8 threads and 137% for 16 threads. adaptSTM offers performance that is competitive with tinySTM for low-contention benchmarks; for high-contention benchmarks adaptSTM outperforms tinySTM. Thread-local adaptation alone increases performance on average by 4.3% for 16 threads, and up to 10% for individual benchmarks, compared to adaptSTM without active adaptation.","PeriodicalId":323366,"journal":{"name":"(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114210096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

VMAD: A virtual machine for advanced dynamic analysis of programs VMAD:用于高级动态分析程序的虚拟机

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762725

A. Jimborean, Matthieu Herrmann, Vincent Loechner, P. Clauss

引用次数: 10

A comprehensive analysis and parallelization of an image retrieval algorithm 一个图像检索算法的综合分析和并行化

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762732

Zhenman Fang, Donglei Yang, Weihua Zhang, Haibo Chen, B. Zang

{"title":"A comprehensive analysis and parallelization of an image retrieval algorithm","authors":"Zhenman Fang, Donglei Yang, Weihua Zhang, Haibo Chen, B. Zang","doi":"10.1109/ISPASS.2011.5762732","DOIUrl":"https://doi.org/10.1109/ISPASS.2011.5762732","url":null,"abstract":"The prevalence of the Internet and cloud computing has made multimedia data, such as image data and video data, become major data types in our daily life. For example, many data-intensive applications, such as health care and video recommendation, involve collecting, indexing and retrieving tera-scale multimedia data every day. With such a huge amount of multimedia data to process, the processing speed has been one of the major challenges to guarantee real-time requirements. The advent of multi-core hardware has opened new opportunities to improve the effectiveness of multimedia data processing. In this paper, we make a comprehensive analysis on different potential parallelism, including pipeline parallelism, task parallelism at both scale level and block level, data parallelism, and their combinations, in a typical image retrieval algorithm called SURF, which is the core algorithm of many multimedia (i.e., image and video) retrieval applications. Experimental results show the following observations of parallelism in SURF: 1) when only one level parallelism is exploited, block-level parallelism is more efficient and scalable than other alternatives; 2) data parallelism cannot be ignored especially when parallel resources increase and 3) the combination of block-level parallelism and pipeline parallelism is the most efficient parallelizing manner for the studied image retrieval algorithm. Based on these observations, we have implemented a parallel image retrieval algorithm. It can be easily mapped onto different multi-core platforms with good scalability. On a commodity server machine with 16-core, the parallel implementation achieves a speedup of 13X, which is 84% faster than P-SURF, a previous state-of-the-art parallelization of SURF on CPU; while on GPGPU, it achieves a speedup of 46X, which is 53% faster than CUDA SURF, a previous state-of-the-art parallelization of SURF on GPGPU.","PeriodicalId":323366,"journal":{"name":"(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131043174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Analyzing throughput of GPGPUs exploiting within-die core-to-core frequency variation 分析利用芯片内核到核频率变化的gpgpu吞吐量

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762740

Jungseob Lee, Paritosh Pratap Ajgaonkar, N. Kim

引用次数: 25

Portable trace compression through instruction interpretation 通过指令解释的便携式跟踪压缩

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762720

Svilen Kanev, R. Cohn

引用次数: 7

Detecting race conditions in asynchronous DMA operations with full system simulation 用全系统模拟检测异步DMA操作中的竞争条件

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762737

M. Kistler, Daniel A. Brokenshire

{"title":"Detecting race conditions in asynchronous DMA operations with full system simulation","authors":"M. Kistler, Daniel A. Brokenshire","doi":"10.1109/ISPASS.2011.5762737","DOIUrl":"https://doi.org/10.1109/ISPASS.2011.5762737","url":null,"abstract":"In this paper, we describe a technique for detecting race conditions between direct memory access (DMA) operations and load/store instructions using a full system simulator. Our approach uses event monitoring features of a full system simulator to monitor DMA operations and the memory areas they access and detect conflicting accesses that could represent races conditions. Our race condition checker tracks DMA operations from the time they are issued until they are architecturally guaranteed to be complete, rather than simply tracking when they actually complete, and thus detects race conditions in programs even when the actual data accesses do not occur out of order. This feature is valuable because the mechanisms for ensuring ordering of asynchronous DMA operations are complex and often poorly understood by application programmers. These DMA operations may conflict with each other or with loads and stores performed by processor that initiated the operations, creating ample opportunity for race conditions to occur. We describe our race condition checker in detail and show how it can be used to easily detect race conditions in DMA operations initiated by special purpose cores.","PeriodicalId":323366,"journal":{"name":"(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133111775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Finding cool code: An analysis of source-level causes of temperature effects 寻找凉爽的代码:对温度影响的源级原因的分析

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762721

Dan Upton, K. Hazelwood

引用次数: 1

Supply voltage emulation platform for DVFS voltage drop compensation explorations 用于DVFS压降补偿探索的电源电压仿真平台

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762727

Andreas Genser, Christian Bachmann, C. Steger, R. Weiss, J. Haid

引用次数: 4

A comparative benchmarking of the FFT on Fermi and Evergreen GPUs FFT在Fermi和Evergreen gpu上的比较基准测试

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762726

Mohamed F. Ahmed, Omar Haridy

引用次数: 5