(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE最新文献_第2页

Trace-driven simulation of multithreaded applications 多线程应用程序的跟踪驱动模拟

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762718

Alejandro Rico, A. Duran, F. Cabarcas, Yoav Etsion, Alex Ramírez, M. Valero

{"title":"Trace-driven simulation of multithreaded applications","authors":"Alejandro Rico, A. Duran, F. Cabarcas, Yoav Etsion, Alex Ramírez, M. Valero","doi":"10.1109/ISPASS.2011.5762718","DOIUrl":"https://doi.org/10.1109/ISPASS.2011.5762718","url":null,"abstract":"Over the past few years, computer architecture research has moved towards execution-driven simulation, due to the inability of traces to capture timing-dependent thread execution interleaving. However, trace-driven simulation has many advantages over execution-driven that are being missed in multithreaded application simulations. We present a methodology to properly simulate multithreaded applications using trace-driven environments. We distinguish the intrinsic application behavior from the computation for managing parallelism. Application traces capture the intrinsic behavior in the sections of code that are independent from the dynamic multithreaded nature, and the points where parallelism-management computation occurs. The simulation framework is composed of a trace-driven simulation engine and a dynamic-behavior component that implements the parallelism-management operations for the application. Then, at simulation time, these operations are reproduced by invoking their implementation in the dynamic-behavior component. The decisions made by these operations are based on the simulated architecture, allowing to dynamically reschedule sections of code taken from the trace to the target simulated components. As the captured sections of code are independent from the parallel state of the application, they can be simulated on the trace-driven engine, while the parallelism-management operations, that require to be re-executed, are carried out by the execution-driven component, thus achieving the best of both trace- and execution-driven worlds. This simulation methodology creates several new research opportunities, including research on scheduling and other parallelism-management techniques for future architectures, and hardware support for programming models.","PeriodicalId":323366,"journal":{"name":"(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125514961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 82

A single-specification principle for functional-to-timing simulator interface design 功能-时序模拟器接口设计的单一规格原则

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762735

D. Penry

{"title":"A single-specification principle for functional-to-timing simulator interface design","authors":"D. Penry","doi":"10.1109/ISPASS.2011.5762735","DOIUrl":"https://doi.org/10.1109/ISPASS.2011.5762735","url":null,"abstract":"Microarchitectural simulators are often partitioned into separate, but interacting, functional and timing simulators. These simulators interact through some interface whose level of detail depends upon the needs of the timing simulator. The level of detail supported by the interface profoundly affects the speed of the functional simulator, therefore, it is desirable to provide only the detail that is actually required. However, as the microarchitectural design space is explored, these needs may change, requiring corresponding time-consuming and error-prone changes to the interface. Thus simulator developers are tempted to include extra detail in the interface \"just in case\" it is needed later, trading off simulator speed for development time. We show that this tradeoff is unnecessary if a single-specification design principle is practiced: write the simulator once with an extremely detailed interface and then derive less-detailed interfaces from this detailed simulator. We further show that the use of an Architectural Description Language (ADL) with constructs for interface specification makes it possible to synthesize simulators with less-detailed interfaces from a highly-detailed specification with only a few lines of code and minimal effort. The speed of the resulting low-detail simulators is up to 14.4 times the speed of high-detail simulators.","PeriodicalId":323366,"journal":{"name":"(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125683481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A dynamic energy management scheme for multi-tier data centers 面向多层数据中心的动态能源管理方案

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762742

Seung-Hwan Lim, Bikash Sharma, Byungchul Tak, C. Das

{"title":"A dynamic energy management scheme for multi-tier data centers","authors":"Seung-Hwan Lim, Bikash Sharma, Byungchul Tak, C. Das","doi":"10.1109/ISPASS.2011.5762742","DOIUrl":"https://doi.org/10.1109/ISPASS.2011.5762742","url":null,"abstract":"Multi-tier data centers have become a norm for hosting modern Internet applications because they provide a flexible, modular, scalable and high performance environment. However, these benefits come at a price of the economic dent incurred in powering and cooling these large hosting centers. Thus, energy efficiency has become a critical consideration in designing Internet data centers. In this paper, we propose a multifaceted approach, Hybrid, consisting of dynamic provisioning, frequency scaling and dynamic power management (DPM) schemes to reduce the energy consumption of multi-tier data centers, while meeting the Service Level Agreements (SLAs). We formulate a mathematical model of the energy and performance/SLA optimization problem followed by a queueing theory based approach to develop two heuristics for solving the optimization problem. The first heuristic dynamically provisions the optimal number of servers required in each tier. The second heuristic proactively decides the CPU speed and the duration of sleep states of a server to achieve further energy savings. We evaluate our heuristics using a simulator that was validated with real measurements on a prototype three-tier data center consisting of 25 servers with two multi-tier application benchmarks. Our experimental results indicate that the proposed scheme, Hybrid, can reduce the energy consumption by 50% relative to static provisioning without CPU frequency scaling and DPM. We demonstrate that Hybrid satisfies the SLAs for dynamically varying workloads. In addition, the proposed multifaceted approach is more energy efficient than the other methods such as dynamic provisioning with exploiting deep sleep states.","PeriodicalId":323366,"journal":{"name":"(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132190161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware 在实际硬件上构建CPI栈的机械经验处理器性能建模

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762738

Stijn Eyerman, Kenneth Hoste, L. Eeckhout

{"title":"Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware","authors":"Stijn Eyerman, Kenneth Hoste, L. Eeckhout","doi":"10.1109/ISPASS.2011.5762738","DOIUrl":"https://doi.org/10.1109/ISPASS.2011.5762738","url":null,"abstract":"Analytical processor performance modeling has received increased interest over the past few years. There are basically two approaches to constructing an analytical model: mechanistic modeling and empirical modeling. Mechanistic modeling builds up an analytical model starting from a basic understanding of the underlying system — white-box approach — whereas empirical modeling constructs an analytical model through statistical inference and machine learning from training data, e.g., regression modeling or neural networks — black-box approach. While an empirical model is typically easier to construct, it provides less insight than a mechanistic model. This paper bridges the gap between mechanistic and empirical modeling through hybrid mechanistic-empirical modeling (gray-box modeling). Starting from a generic, parameterized performance model that is inspired by mechanistic modeling, regression modeling infers the unknown parameters, alike empirical modeling. Mechanistic-empirical models combine the best of both worlds: they provide insight (like mechanistic models) while being easy to construct (like empirical models). We build mechanistic-empirical performance models for three commercial processor cores, the Intel Pentium 4, Core 2 and Core il, using SPEC CPU2000 and CPU2006, and report average prediction errors between 9% and 13%. In addition, we demonstrate that the mechanistic-empirical model is more robust and less subject to overfitting than purely empirical models. A key feature of the proposed mechanistic-empirical model is that it enables constructing CPI stacks on real hardware, which provide insight in commercial processor performance and which offer opportunities for software and hardware optimization and analysis.","PeriodicalId":323366,"journal":{"name":"(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126125302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 39

Universal rules guided design parameter selection for soft error resilient processors 通用规则指导软误差弹性处理器的设计参数选择

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762741

Lide Duan, Ying Zhang, Bin Li, Lu Peng

{"title":"Universal rules guided design parameter selection for soft error resilient processors","authors":"Lide Duan, Ying Zhang, Bin Li, Lu Peng","doi":"10.1109/ISPASS.2011.5762741","DOIUrl":"https://doi.org/10.1109/ISPASS.2011.5762741","url":null,"abstract":"High-performance processors suffer from soft error vulnerability due to the increasing on-chip transistor density, shrinking processor feature size, lower threshold voltage, etc. In this paper, we propose to use a rule search strategy, i.e. Patient Rule Induction Method (PRIM), to optimize processor soft error robustness. By exploring a huge microarchitectural design space on the Architectural Vulnerability Factor (AVF), we are capable of generating a set of selective rules on key design parameters. Applying these rules at early design stage effectively identifies the configurations that are inherently reliable to soft errors. Furthermore, we propose a generic approach capable of generating a set of “universal” rules that achieves the optimization of the output variable for different programs in execution. The effectiveness of the universal rule set is validated on programs that are not used in training. This cross-program capability is very useful in the era of multi-threading. Finally, the proposed scheme is extended to multiprocessors where multiple design metrics including reliability, performance and power are balanced. Our proposed methodology is able to generate quantitative and universal solutions for both uniprocessors and multiprocessors.","PeriodicalId":323366,"journal":{"name":"(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127186198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Accelerating search and recognition workloads with SSE 4.2 string and text processing instructions 使用SSE 4.2字符串和文本处理指令加速搜索和识别工作负载

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762731

Guangyu Shi, Min Li, Mikko H. Lipasti

{"title":"Accelerating search and recognition workloads with SSE 4.2 string and text processing instructions","authors":"Guangyu Shi, Min Li, Mikko H. Lipasti","doi":"10.1109/ISPASS.2011.5762731","DOIUrl":"https://doi.org/10.1109/ISPASS.2011.5762731","url":null,"abstract":"Today's information is increasing rapidly, doubling every three years. Consequently, the search and recognition stages in computer applications will consume a growing portion of the total CPU time. The SSE 4.2 instruction set, first implemented in Intel's Core i7, provides string and text processing instructions (STTNI) that utilize SIMD operations for processing character data. Though originally conceived for accelerating string, text, and XML processing, the powerful new capabilities of these instructions are useful outside of these domains, and it is worth revisiting the search and recognition stages of numerous applications to utilize STTNI to improve performance. In this paper, we explored the feasibility and potential benefit of using STTNI to improve the CPU and memory performance of search-and-recognition applications. We optimized four benchmark applications — cache simulation, B+tree search algorithm, template matching, Basic Local Alignment Search Tool (BLAST) — with STTNI, and the new applications outperform their respective original implementations by a factor of 1.4× to 13×.","PeriodicalId":323366,"journal":{"name":"(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126034276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Characterization and dynamic mitigation of intra-application cache interference 应用内部缓存干扰的表征和动态缓解

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762710

Carole-Jean Wu, M. Martonosi

{"title":"Characterization and dynamic mitigation of intra-application cache interference","authors":"Carole-Jean Wu, M. Martonosi","doi":"10.1109/ISPASS.2011.5762710","DOIUrl":"https://doi.org/10.1109/ISPASS.2011.5762710","url":null,"abstract":"Given the emerging dominance of CMPs, an important research problem concerns application memory performance in the face of deep memory hierarchies, where one or more caches are shared by several cores. In current systems, many factors can cause interference in the shared last-level cache (LLC). While predicting an application's memory performance is difficult enough in an idealized setup, it becomes even more complicated in real-machine environments in which interference can stem from operating system memory accesses, and even from an application's own prefetch requests and page table walks caused by TLB misses. This paper characterizes the degree by which intra-application interference factors such as page table walks and hardware prefetching influence performance. Using hardware performance counters on an Intel platform, we first characterize real-system LLC interference and show that application data memory references represent much less than half of the LLC misses, with hardware prefetching and page table walks causing considerable LLC interference. Based on these characterizations, we propose dynamic management methods to reduce intra-application interference. First, we evaluate a dynamic OS-reference-aware cache insertion policy that reduces interference and improves user IPCs by as much as 19% (5% on average). Second, to mitigate prefetch-induced LLC interference, we propose, implement, and evaluate an automatic prefetch manager that uses Intel PEBS capabilities to dynamically estimate prefetch-induced interference and accordingly adjust the aggressiveness of hardware prefetchers as programs run. Overall, our characterizations are important in highlighting the challenges of intra-application interference, and our hardware and software proposals offer significant solutions for addressing them.","PeriodicalId":323366,"journal":{"name":"(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128110933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 53

A reconfigurable simulator for large-scale heterogeneous multicore architectures 面向大规模异构多核体系结构的可重构模拟器

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762722

Jiayuan Meng, K. Skadron

引用次数: 9

A semi-preemptive garbage collector for solid state drives 固态驱动器的半抢占式垃圾收集器

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762711

Junghee Lee, Youngjae Kim, G. Shipman, S. Oral, Feiyi Wang, Jongman Kim

{"title":"A semi-preemptive garbage collector for solid state drives","authors":"Junghee Lee, Youngjae Kim, G. Shipman, S. Oral, Feiyi Wang, Jongman Kim","doi":"10.1109/ISPASS.2011.5762711","DOIUrl":"https://doi.org/10.1109/ISPASS.2011.5762711","url":null,"abstract":"NAND flash memory is a preferred storage media for various platforms ranging from embedded systems to enterprise-scale systems. Flash devices do not have any mechanical moving parts and provide low-latency access. They also require less power compared to rotating media. Unlike hard disks, flash devices use out-of-update operations and they require a garbage collection (GC) process to reclaim invalid pages to create free blocks. This GC process is a major cause of performance degradation when running concurrently with other I/O operations as internal bandwidth is consumed to reclaim these invalid pages. The invocation of the GC process is generally governed by a low watermark on free blocks and other internal device metrics that different workloads meet at different intervals. This results in I/O performance that is highly dependent on workload characteristics. In this paper, we examine the GC process and propose a semi-preemptive GC scheme that can preempt on-going GC processing and service pending I/O requests in the queue. Moreover, we further enhance flash performance by pipelining internal GC operations and merge them with pending I/O requests whenever possible. Our experimental evaluation of this semi-preemptive GC sheme with realistic workloads demonstrate both improved performance and reduced performance variability. Write-dominant workloads show up to a 66.56% improvement in average response time with a 83.30% reduced variance in response time compared to the non-preemptive GC scheme.","PeriodicalId":323366,"journal":{"name":"(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122275431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 68

PRISM: Zooming in persistent RAM storage behavior PRISM:放大持久RAM存储行为

(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE Pub Date : 2011-04-10 DOI: 10.1109/ISPASS.2011.5762712

J. Jung, Sangyeun Cho

{"title":"PRISM: Zooming in persistent RAM storage behavior","authors":"J. Jung, Sangyeun Cho","doi":"10.1109/ISPASS.2011.5762712","DOIUrl":"https://doi.org/10.1109/ISPASS.2011.5762712","url":null,"abstract":"It has been foreseen that some of the roles assumed by conventional rotating hard disk drives (HDDs) will migrate to solid-state drives (SSDs) and emerging persistent RAM storages. New persistent RAM storages have critical advantages over HDDs and even SSDs in terms of performance and power. Persistent RAM technologies are flexible enough to be used for both storage and main memory — in future platforms, this flexibility will allow tighter integration of a system's memory and storage hierarchy. On the other hand, designers are faced with new technical issues to address to fully exploit the benefits of persistent RAM technologies and hide their downsides. In this paper, we introduce PRISM (PeRsIstent RAM Storage Monitor) — our novel infrastructure that enables exploring various design trade-offs of persistent RAM storage. PRISM allows designers to examine a persistent RAM storage's low-level behavior and evaluate its various architectural organizations while running realistic workloads, as well as storage activities of a contemporary off-the-shelf OS. PRISM builds on kernel source code level instrumentation and the standard Linux device driver mechanism to generate persistent RAM storage traces. Moreover, PRISM includes a storage architecture simulator to faithfully model major persistent RAM storage hardware components. To illustrate how and with what PRISM can help the user, we present a case study that involves running an OLTP (on-line transaction processing) workload. PRISM successfully provides the detailed performance analysis results, while incurring acceptable overheads. Based on our experience, we believe that PRISM is a versatile tool for exploring persistent RAM storage design choices ranging from OS-level resource management policy down to chip-level storage organization.","PeriodicalId":323366,"journal":{"name":"(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124881029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2