2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)最新文献

Memory Circuits using Resonant Charge-based Devices 使用共振电荷基器件的存储电路

2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2018-11-01 DOI: 10.1109/DCAS.2018.8620114

N. Sharma, A. Marshall, F. Register, Jin Woong Kwak

引用次数: 1

A Broadband Spectrum Channelizer with PWM-LO Based Sub-Band Equalization 基于PWM-LO子带均衡的宽带频谱信道器

2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2018-11-01 DOI: 10.1109/DCAS.2018.8620186

Ki Yong Kim, Heechai Kang, V. Singh, R. Gharpurey

引用次数: 1

A Dynamic ReLU on Neural Network 基于神经网络的动态ReLU

2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2018-11-01 DOI: 10.1109/DCAS.2018.8620116

Jiong Si, Sarah L. Harris, E. Yfantis

引用次数: 20

A Mixed-Mode Variable Gain Amplifier for Hearing Aid Devices 助听器用混合模式可变增益放大器

2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2018-11-01 DOI: 10.1109/DCAS.2018.8620180

M. Chilukuri, Sungyong Jung

引用次数: 3

Inductor-free Chua’s Circuit Employing Linear Voltage-controlled Resistor 采用线性压控电阻的无电感蔡氏电路

2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2018-11-01 DOI: 10.1109/DCAS.2018.8620179

Sen Li, B. Fahimi

引用次数: 2

A Differential Low-Power Voltage-Clamped ISFET Topology for Biomedical Applications 生物医学应用的差分低功率电压箝位ISFET拓扑

2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2018-11-01 DOI: 10.1109/DCAS.2018.8620183

Shaghayegh Aslanzadeh, A. Hedayatipour, Mst Shamim Ara Shawkat, N. Mcfarlane

引用次数: 1

Memory Optimization Techniques for FPGA based CNN Implementations 基于FPGA的CNN实现内存优化技术

2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2018-11-01 DOI: 10.1109/DCAS.2018.8620112

Masoud Shahshahani, Pingakshya Goswami, D. Bhatia

{"title":"Memory Optimization Techniques for FPGA based CNN Implementations","authors":"Masoud Shahshahani, Pingakshya Goswami, D. Bhatia","doi":"10.1109/DCAS.2018.8620112","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620112","url":null,"abstract":"Deep Learning has played an important role in the classification of images, speech recognition, and natural language processing. Traditionally, these learning algorithms are implemented in clusters of CPUs and GPUs. But with the increase in data size, the models created on CPUs and GPUs are not scalable. Hence we need a hardware model which can be scaled beyond current data and model sizes. This is where FPGA comes into place. With the advancement of CAD tools for FPGAs, the designers do not need to create the architectures of the networks in RTL level using HDLs like Verilog and VHDL. They can use High-level Language like C or C++ to build the models using tools like Xilinx Vivado HLS. Also, the power consumption of FPGA based models for deep learning is substantially low as compared to GPUs. In this paper, we have done an extensive survey of various implementations of FPGA based deep learning architectures with emphasis on Convolutional Neural Networks (CNN). The CNN architectures presented in the literature consume large memory for the storage of weights and images. It is not possible to store this information in the internal FPGA Block RAM. This paper presents comprehensive servery of the methods and techniques used in literatures to tackle the memory consumption issue and how the data movement between high storage external DDR memory and internal BRAM can be reduced.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114729699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Biomimetic, Soft-Material Synapse for Neuromorphic Computing: from Device to Network 仿生软材料突触用于神经形态计算:从设备到网络

2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2018-11-01 DOI: 10.1109/DCAS.2018.8620187

Md. Sakib Hasan, Catherine D. Schuman, J. Najem, Ryan Weiss, Nicholas D. Skuda, A. Belianinov, C. Collier, Stephen A. Sarles, G. Rose

{"title":"Biomimetic, Soft-Material Synapse for Neuromorphic Computing: from Device to Network","authors":"Md. Sakib Hasan, Catherine D. Schuman, J. Najem, Ryan Weiss, Nicholas D. Skuda, A. Belianinov, C. Collier, Stephen A. Sarles, G. Rose","doi":"10.1109/DCAS.2018.8620187","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620187","url":null,"abstract":"Neuromorphic computing refers to a variety of brain-inspired computers, devices, and models inspired by the interconnectivity, performance, and energy efficiency of the human brain. Unlike the ubiquitous von Neumann computer architectures with complex processor cores and sequential computation, biological neurons and synapses operate by storing and processing information simultaneously with the capacity of flexible adaptation resulting in massive computational capability with much less power consumption. The search for a synaptic material which can closely imitate bio-synapse has led to an alamethicin-doped, synthetic biomembrane which can emulate key synaptic functions due to generic memristive property enabling learning and computation. This two-terminal, biomolecular memristor, in contrast to its solid-state counterparts, features similar structure, switching mechanism, and ionic transport modality as biological synapses while consuming considerably lower power. In this paper, we outline a methodology for using this biomolecular synapse to build neural networks capable of solving real-world problems. The physical mechanism underlying its volatile memristance is explored followed by the development of a model of this device for circuit simulation. We outline a circuit design technique to integrate this synapse with solid-state neuron circuit for hardware implementation. Based on these results, we develop a high level simulation framework and use a training scheme called Evolutionary Optimization for Neuromorphic System (EONS) to generate networks for solving two problems, namely iris dataset classification and EEG classification task. The small network size and comparable to state-of-the-art accuracy of these preliminary networks show its potential to enhance synaptic functionality in next generation neuromorphic hardware.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122526954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Deep Learning-Based Person Detection and Classification for Far Field Video Surveillance 基于深度学习的远场视频监控人物检测与分类

2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2018-11-01 DOI: 10.1109/DCAS.2018.8620111

H. Wei, M. Laszewski, N. Kehtarnavaz

引用次数: 33

A Novel Digital Architecture for Gain and Phase Measurements for DC-DC Converters 一种用于DC-DC变换器增益和相位测量的新型数字结构

2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2018-11-01 DOI: 10.1109/DCAS.2018.8620178

Sameer Arora, P. Balsara, D. Bhatia, P. Buck

{"title":"A Novel Digital Architecture for Gain and Phase Measurements for DC-DC Converters","authors":"Sameer Arora, P. Balsara, D. Bhatia, P. Buck","doi":"10.1109/DCAS.2018.8620178","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620178","url":null,"abstract":"The proposed gain and phase (GAP) measurement architecture is a digitally-implemented device, which is used to measure the gain and phase of DC-DC voltage converters. The device excites the system under test with a small-signal sinusoidal test signal and measures both the time histories of the test signal and the response signal. The device sweeps different frequency points using the direct-digital-synthesis (DDS) technique. Further, to achieve a wide dynamic range, the phase and amplitude response (Bode plot) are calculated using the Lock-in amplifier technique. The device has the flexibility of sampling the response in either the off-time, the on-time or at any other time (average) sampling of the power switch for the DC-DC converter. Furthermore, the proposed system is integrated with a graphical user interface (GUI) which communicates with the device. Through the GUI the user may select to perform measurements such as the transfer function of the plant, the open loop and the closed loop of the controller, measurement of audio susceptibility, total harmonic distortion and noise (THD+N) and ripple spectrum. The GUI can also be used to design a Pulse Width Modulation (PWM) linear controller on the fly, estimating the open loop response T(s), the closed loop response T(s)/(1+T(s)) and the inverse loop response 1/T(s). Analysis of the proposed system is provided, alongside with various applications and experimental results.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"194-199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130699141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1