S. R. Rupanagudi, Varsha G. Bhat, B. Ranjani, S. Eshwari, S. Shreyas, M. N. Vishnu, R. K. Singh, Sukanya Singh, B. Chandrashekar
{"title":"A further simplified algorithm for blink recognition using video oculography for communicating","authors":"S. R. Rupanagudi, Varsha G. Bhat, B. Ranjani, S. Eshwari, S. Shreyas, M. N. Vishnu, R. K. Singh, Sukanya Singh, B. Chandrashekar","doi":"10.1109/IBSS.2015.7456643","DOIUrl":"https://doi.org/10.1109/IBSS.2015.7456643","url":null,"abstract":"A lot of research has been carried out in the past decade to assist patients suffering from paralysis or Motor Neuron Disease (MND) to communicate and also to move. Though solutions exist, they are extremely expensive and also sluggish in user response. This paper presents a cost effective setup and a novel algorithm to help the MND affected segment of the society to communicate using only blinks. A major feature of the research carried out is the high speed dilation algorithm discovered and also a simplified eye detection methodology, which is totally independent of a computer interface. All experiments were carried out using Simulink bundled with MATLAB 2011b. A Java implementation for speed efficiency calculation was also carried out and proved that the proposed methodology is 8 times faster compared to its predecessor technology.","PeriodicalId":317804,"journal":{"name":"2015 IEEE Bombay Section Symposium (IBSS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132262534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"VHDL implementation of Discrete Hartley Transform using Urdhwa multiplier","authors":"Shirali Parsai, Swapnil Jain, Jyoti Dangi","doi":"10.1109/IBSS.2015.7456665","DOIUrl":"https://doi.org/10.1109/IBSS.2015.7456665","url":null,"abstract":"Discrete Hartley Transform (DHT) is one of the transform used for converting data in time domain into frequency domain using only real values. DHT can be used for highly modular and parallel processing of data in VLSI applications. We have proposed a new algorithm for calculating DHT of length 2N, where N=3 and 4. We have implemented multiplier as an improvement in place of simple multiplication used in conventional DHT. This paper gives a comparison between conventional DHT algorithm and proposed DHT algorithm in terms of delays and area.","PeriodicalId":317804,"journal":{"name":"2015 IEEE Bombay Section Symposium (IBSS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117289193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Designing an accelerated hardware architecture for polynomial matrix multiplications","authors":"K. S. Bodani, A. Kumbhar","doi":"10.1109/IBSS.2015.7456663","DOIUrl":"https://doi.org/10.1109/IBSS.2015.7456663","url":null,"abstract":"In this project, reconfigurable hardware architecture is used for performing the polynomial matrix multiplications (PMM). Hardware architecture is designed by using the Xilinx system generator tool. System generator enables the use of the math works model-based Simulink design environment for FPGA design. For designing PMM system, Fast Fourier Transform (FFT) technique is used rather than Convolution technique, because convolution takes computational time more than FFT. It's easy to implement the generic structure of FFT. This project implements the sharpening, smoothing, blurring and Gaussian smooth application using polynomial matrix multiplication. The hardware implementation is possible by using field-programmable array architecture. This PMM system takes less time for execution and it uses less FPGA resources like number of slice registers, number of slice LUT's, the number of block RAM/FIFO and number of bonded IOBs. The architecture for computing the PMM is implemented on Virtex-5.","PeriodicalId":317804,"journal":{"name":"2015 IEEE Bombay Section Symposium (IBSS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114425177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Periodical correlation analysis of digital data pulses for real-time medical applications","authors":"P. S. Abdul Lateef Haroon, Fathima Jabeen","doi":"10.1109/IBSS.2015.7456662","DOIUrl":"https://doi.org/10.1109/IBSS.2015.7456662","url":null,"abstract":"The main aim of the biomedical signal processing is to extract information from a biological signal. Biomedical signal processing involves recording of the biological events such as heart-beats etc. The feasibility of extracting accurate Heart-Rate is demonstrated by measuring the variability in the photoelectric plethysmography signals. The Pulse Rate is obtained from the systolic peaks of the pulse wave measured from a Heart-Beat sensor. From the Pulse Rate the Heart-Rate can be calculated. Digital Data Processing system involves real-time processing of Heart-Beat pulses. The captured data is processed in real time using Pulse Shape Discrimination Algorithm and verified on a field programmable gate array device. This study opens a way to derive heart rate from pulse rate with a simple assessment which can be applied to many persons suffering with various heart diseases. It is also analyzed the various distorted signals caused by motion artifacts are removed using morphological operators such as erosion and dilation without the help of any filters, and designed a PSD algorithm to calibrate the signals for better accuracy. The main focus is on the operation of Correlation with which the PSD has been designed. The proposed Algorithm is designed using Xilinx ISE 13.4.","PeriodicalId":317804,"journal":{"name":"2015 IEEE Bombay Section Symposium (IBSS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125923833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}